STV0974E datasheet(25/69 Pages) STMICROELECTRONICS

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Functional description

STV0974

25/61

Interrupt Mask Register (IMASK)

Interrupt Clear Register (ICLR)

FIFO Threshold Register (FTHR)

This register is used to program values such as 1 (flush), 16 or 32 (DMA burst) or any greater value

up to 2032 for interrupt driven data transfer. Note that for proper DMA operation, ‘threshold’ must be

greater than or equal to the DMA burst size (MICR[BSIZE]).

Table 16: Interrupt Mask Register

Bits

Name

Type

Description

[7:6]

Reserved

[5:0]

IMASK

Each IMASK bit set to ‘1’ enables the corresponding interrupt source bit in the status

Table 17: Interrupt Clear Register

Bits

Name

Type

Description

[7:6]

Reserved

[5:2]

ICLR

Each ICLR bit written with a ‘1’ clears the corresponding interrupt source bit in the

status register (SR). Writing a ‘0’ has no effect

[1:0]

Reserved

Table 18: FIFO threshold register

Description

FTRH

Holds the FIFO threshold value

NE = 1

threshold = 1

(TH is ignored)

NE = 0

threshold = TH * 16

(TH valid range is [1, 2...127])

Table 19: FIFO Threshold Register

Bits

Name

Type

Description

[15:11]

Reserved

[10:4]

Threshold value in 16-byte increments.

[3:1]

Reserved

Not Empty:

1 = Force threshold to 1 (TH is ignored)

0 = Normal

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