CS42516 datasheet(69/90 Pages) CIRRUS

69 / 90 page

DS583F1

CS42516

the status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence

will not appear in the receiver error register, will not affect the RERR interrupt, and will not affect the

current audio sample. The CCRC and QCRC bits behave differently from the other bits: they do not

affect the current audio sample even when unmasked.

6.27

Mutec Pin Control (address 28h)

6.27.1 MUTEC POLARITY SELECT (MCPOLARITY)

Default = 0

0 - Active low

1 - Active high

Function:

Determines the polarity of the MUTEC pin.

6.27.2 CHANNEL MUTES SELECT (M_AOUTXX)

Default = 1111

0 - Channel mute is not mapped to the MUTEC pin

1 - Channel mute is mapped to the MUTEC pin

Function:

Determines which channel mutes will be mapped to the MUTEC pin. If no channel mute bits are

mapped, then the MUTEC pin is driven to the “active” state as defined by the POLARITY bit. These

Channel Mute Select bits are “ANDed” together in order for the MUTEC pin to go active. This means

that if multiple Channel Mutes are selected to be mapped to the MUTEC pin, all corresponding chan-

nels must be muted before the MUTEC will go active.

6.28

RXP/General-Purpose Pin Control (addresses 29h to 2Fh)

6.28.1 MODE CONTROL (MODEX)

Default = 00

00 - RXP Input

01 - Mute Mode

10 - GPO/Overflow Mode

11 - GPO, Drive High Mode

Function:

RXP Input - The pin is configured as a receiver input which can then be muxed to either the TXP pin

or to the internal receiver.

Mute Mode - The pin is configured as a dedicated mute pin. The muting function is controlled by the

Function bits.

GPO, Drive Low / ADC Overflow Mode - The pin is configured as a general-purpose output driven low

432

Reserved

MCPolarity

M_AOUTA1

M_AOUTB1

M_AOUTA2

M_AOUTB2

M_AOUTA3

M_AOUTB3

Reserved

432

Mode1

Mode0

Polarity

Function4

Function3

Function2

Function1

Function0

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