CS5461 datasheet(39/46 Pages) CIRRUS

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CS5461

DS546PP2

7.12 PulseRateF Register

Address: 18

Default** = 32000.00 Hz

The PulseRateF Register sets the average pulse frequency of the FOUT output pin. The register’s smallest valid

value is 2-4 but can be in 2-5 increments. A pulserate higher than MCLK/K/8 will result in a pulse rate setting of

MCLK/K/8.

7.13 Temperature Sensor Output Register

Address: 19

This signed register contains the output of the On-Chip Temperature Sensor. The results are in the range of

-128.0

≤ T < 128.0. The value is represented in unsigned binary notation, with the binary point place to the left

of the MSB. This result is updated after each computation cycle.

7.14 Pulsewidth

Address: 21

Default** = 512 sample periods

This signed register determines the pulsewidth of EOUT and EDIR pulses in Mechanical Counter Mode. The

width is set in number of sample periods. The default is 512. This corresponds to a pulsewidth of

512 samples / [(MCLK/K)/1024] = 128 msec with MCLK = 4.096 MHz and K = 1. Although this is a signed reg-

ister a negative value will have no meaning; pulsewidth settings must be positive.

7.15 VSAGLevel: Voltage Sag-Detect Threshold Level

Address: 23

Default** = 0x000000

This signed register sets the threshold level for the Voltage Sag Detect feature. To activate the VSAG bit the

Status Register, the value of the VRMS register must remain below this threshold level for a set number of sam-

ples (defined in the VSAGDuration Register). Voltage threshold levels must be positive values; a negative value

can be used to disable the feature. For more information about the voltage sag detect functionality, refer to Sec-

tion 4.10 of the data sheet.

MSB

LSB

218

217

216

215

214

213

212

211

.....

2-1

2-2

2-3

2-4

2-5

MSB

LSB

-(27)26

.....

2-10

2-11

2-12

2-13

2-14

2-15

2-16

MSB

LSB

223

222

221

220

219

218

217

216

.....

MSB

LSB

-(20)2-1

2-2

2-3

2-4

2-5

2-6

2-7

.....

2-17

2-18

2-19

2-20

2-21

2-22

2-23

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