CS5461 datasheet(35/46 Pages) CIRRUS

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CS5461

DS546PP2

0 = High-pass filter disabled (default)

1 = High-pass filter enabled

iCPU

Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals

are sampled, the logic driven by CPUCLK should not be active during the sample edge.

0 = normal operation (default)

1 = minimize noise when CPUCLK is driving rising edge logic

K[3:0]

Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal

clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-

tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero).

7.2 DC Current Offset Register and DC Voltage Offset Register

Address: 1 (DC Current Offset Register); 3 (DC Voltage Offset Register)

Default** = 0.000

The DC Offset Registers are initialized to zero on reset, allowing for uncalibrated normal operation. If DC Offset

Calibration is performed, this register is updated after one computation cycle with the current or voltage offset if

the proper DC input signals are applied. DRDY will be asserted at the end of the calibration. This register may

be read and stored for future system offset compensation. The value is in the range ± full scale. The numeric

format of this register is two’s complement notation.

7.3 AC/DC Current Gain Register and AC/DC Voltage Gain Register

Address: 2 (Current Gain Register); 4 (Voltage Gain Register)

Default** = 1.000

The Gain Registers are initialized to 1.0 on reset, allowing for uncalibrated normal operation. The Gain registers

hold the result of either the AC or DC gain calibrations, whichever was most recently performed. If DC calibration

is performed, the register is updated after one computation cycle with the system gain when the proper DC input

is applied. If AC calibration is performed, then after ~(6N + 30) A/D conversion cycles (where N is the value of

the Cycle-Count Register) the register(s) is updated with the system gain when the proper AC input is applied.

DRDY will be asserted at the end of the calibration. The register may be read and stored for future system gain

compensation. The value is in the range 0.0

≤ Gain < 3.9999.

7.4 Cycle Count Register

Address: 5

Default** = 4000

The Cycle Count Register value (denoted as ‘N’) determines the length of one energy and RMS computation

cycle. During continuous conversions, the computation cycle frequency is (MCLK/K)/(1024

∗N).

MSB

LSB

-(20)2-1

2-2

2-3

2-4

2-5

2-6

2-7

.....

2-17

2-18

2-19

2-20

2-21

2-22

2-23

MSB

LSB

2-1

2-2

2-3

2-4

2-5

2-6

.....

2-16

2-17

2-18

2-19

2-20

2-21

2-22

MSB

LSB

223

222

221

220

219

218

217

216

.....

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