CD1283 datasheet(19/94 Pages) INTEL

19 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

4.0

Local CPU communication with the CD1283 occurs through a register set. Within this register set,

there are four types of registers:

• Global, common to all functions of the device

• Parallel pipeline

• Parallel port

• Service-acknowledge accessible

Global registers are always available to the CPU and their addresses are not affected by the

contents of the AER (this register is provided to maintain compatibility with the CD1284).

Note:

AER must be set to ‘00h’ and must not be changed (except to access RCR), or access to many

registers will not work properly!

The following tables define the register names, read and write access modes, internal address

offsets, and bit definitions. A detailed description of each register, its contents and functions can be

found in Chapter 7.0 The address offset defined is the binary value that should be applied to the

address inputs (A[6:0]) during I/O cycles.

Note that the addresses are shown relative to the CD1283 definition of address lines. In 16- and 32-

bit systems, it is a common practice to connect 8-bit peripherals to only one byte lane. Thus, in 16-

bit systems, the CD1283 appears at every other address (for example, the CD1283 A[0] input is

connected to CPU A[1]). In 32-bit systems, the CD1283 appears at every fourth address (CD1283

A[0] is connected to CPU A[2]). In either of these cases, the address used by the programmer will

be different than what is shown in the tables. For instance, in a 16-bit Motorola 68000-based

system, the CD1283 is placed on data lines D[7:0], which are at odd addresses in the Motorola

scheme of addressing. The CD1283 A[0] input is connected with A[1] of the 68000, A[1] with

A[2], and so on. Thus, the CD1283 address 0x40 becomes 0x81 to the programmer. It is left-

shifted one bit and A[0] must be ‘1’ for low-byte (D[7:0]) accesses.

4.1

Table 1.

Global Registers

Name

Hex

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

AER

Poll

GFRCR

Firmware Revision Code

GPDIR

Dir 7

Dir 6

Dir 5

Dir 4

Dir 3

Dir 2

Dir 1

Dir 0

GPIO

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

PIR

PPIreq

PPort

Pipeline

PPR

Binary Value

SVRR

DMAREQ

n/u

SRP

n/u

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