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DLP4710AFQL bảng dữ liệu(PDF) 35 Page - Texas Instruments

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tên linh kiện DLP4710AFQL
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DLP4710AFQL bảng dữ liệu(HTML) 35 Page - Texas Instruments

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DLP4710
www.ti.com
DLPS125 – NOVEMBER 2018
Product Folder Links: DLP4710
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
10 Layout
10.1 Layout Guidelines
There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board
connector to a flex cable. Flex cable provides the interface of data and Ctrl signals between the DLPC343x
controller and the DLP4710 DMD. For detailed layout guidelines refer to the layout design files. Some layout
guideline for the flex cable interface with DMD are:
•
Match lengths for the LS_WDATA and LS_CLK signals.
•
Minimize vias, layer changes, and turns for the HS bus signals. Refer Figure 24.
•
Minimum of two 220-nF decoupling capacitor close to VBIAS. Capacitor C3 and C10 in Figure 24.
•
Minimum of two 220-nF decoupling capacitor close to VRST. Capacitor C1 and C9 in Figure 24.
•
Minimum of two 220-nF decoupling capacitor close to VOFS. Capacitor C2 and C8 in Figure 24.
•
Minimum of four 220-nF decoupling capacitor close to VDDI and VDD. Capacitor C4, C5, C6 and C7 in
Figure 24.
10.2 Layout Example
Figure 24. Power Supply Connections



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