AD5683R/AD5682R/AD5681R/AD5683

Data Sheet

Rev. D | Page 10 of 28

10

9

SDI

8

SYNC

7

SCLK

6

AD5683R/

AD5681R

TOP VIEW

(Not to Scale)

10

9

SDI

8

SYNC

7

SCLK

6

AD5683R-3

TOP VIEW

(Not to Scale)

Figure 10. Pin Configuration, 10-Lead MSOP, SDO Option

Table 8. Pin Function Descriptions, 10-Lead MSOP

SDO

Mnemonic

Description

1

1

Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple this pin to GND.

2

N/A

Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple this pin to GND.

3

2

RESET

Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and

external pins are ignored. The input and DAC registers are loaded with a zero-scale value, and the write

N/A

3

SDO

Serial Data Output. Can be used for daisy chaining or readback commands.

4

4

LDAC

Load DAC. Transfers the content of the input register to the DAC register. It can be operated in

asynchronous mode (see Figure 4). This pin can be tied permanently low; in this case, the DAC register is

automatically updated when new data is written to the input register.

5

5

GND

Ground Reference.

6

6

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates of up to 50 MHz.

7

7

SYNC

Synchronization Data Input. When SYNC goes low, it enables the SCLK and SDI buffers and the input

shift register.

8

8

SDI

Serial Data Input. Data is sampled on the falling edge of SCLK.

9

9

Reference Input/Output. When using the internal reference, this is the reference output pin. The default

for this pin is as a reference output. It is recommended that this pin be decoupled to GND with a 10 nF

capacitor.

10

10

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.