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XUJ736125K bảng dữ liệu(PDF) 8 Page - Integrated Device Technology

tên linh kiện XUJ736125K
Giải thích chi tiết về linh kiện  XU Family of Low Phase Noise Quartz-based PLL Oscillators
PDF  21 Pages
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nhà sản xuất  IDT [Integrated Device Technology]
Trang chủ  http://www.idt.com
Logo IDT - Integrated Device Technology

XUJ736125K bảng dữ liệu(HTML) 8 Page - Integrated Device Technology

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©2018 Integrated Device Technology, Inc.
June 25, 2018
XU Datasheet
T a ble 1 5 . 1 .8 V AC Ele c t ric a l Cha ra c t e rist ic s
VDD = 1.8V ±5%, TA = -20°C to +70°C; -40°C to +85°C, -40°C to +105°C.
Symbol
Parameter
Test Condition
Minimum
Typical
Maximum
Units
F
Output Frequency Range
LVDS.
0.016
1000
MHz
LVPECL, HCSL.
0.016
670
LVCMOS.
0.016
125
Frequency Stability
Temperature = -20°C to +70°C.
±20
±100
ppm
Temperature = -40°C to +85°C.
±25
±100
ppm
Temperature = -40°C to +105°C.
±50
±100
ppm
Aging (1st year)
TA = 25°C.
±3
Aging (10 years)
TA = 25°C.
±10
Output Load
LVDS.
Differential.
100
Ω
LVPECL, HCSL.
To GND.
50
LVCMOS.
To GND.
10
pF
TST
Start-up Time
Output valid time after VDD meets minimum
specified level.
10
ms
tR
Output Rise Time
LVDS.
20% to 80% Vpk-pk.
250
315
ps
LVPECL.
250
350
HCSL.
320
LVCMOS.
10% to 90% VDD.
5ns
tF
Output Fall Time
LVDS.
80% to 20% Vpk-pk.
250
315
ps
LVPECL.
250
350
HCSL.
320
LVCMOS.
90% to 10% VDD.
5ns
ODC
Output Clock Duty Cycle
LVDS.
FOUT < 156.25MHz.
45
55
%
FOUT < 156.25MHz.
40
60
LVPECL.
FOUT < 312.5MHz.
45
55
FOUT > 312.5MHz.
40
60
HCSL.
40
60
LVCMOS.
FOUT < 62.5MHz.
45
55
FOUT > 62.5MHz.
40
60
TOE
Output Enable/ Disable Time
100
ns
fJITTER
Phase Jitter
(12kHz–20MHz)
LVDS.
800
1200
fsec
LVPECL.
750
1200
HCSL.
100
1200
LVCMOS.
FOUT = 100MHz.
800
1200



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