2

Integrated

Circuit

Systems, Inc.

ICS954204

0933D—03/16/05

Pin Description

PIN # PIN NAME

PIN TYPE DESCRIPTION

1

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

2

GND

PWR

Ground pin.

3

PCICLK3

OUT

PCI clock output.

4

PCICLK4

OUT

PCI clock output.

5

PCICLK5

OUT

PCI clock output.

6

GND

PWR

Ground pin.

7

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

8

ITP_EN/PCICLK_F0

I/O

Free running PCI clock not affected by PCI_STOP#.

ITP_EN: latched input to select pin functionality

1 = CPU_ITP pair

0 = SRC pair

9

*SELSRC_LCDCLK#/PCICLK_F1

I/O

Latched input select for LCD_ss/ SRCCLK output frequency:

0 = LCD,

1 = SRCCLK/ 3.3V free-running PCI clock output.

10

Vtt_PwrGd#/PD

IN

Vtt_PwrGd# is an active low input used to determine when latched inputs

are ready to be sampled. PD is an asynchronous active high input pin used

to put the device into a low power state. The internal clocks, PLLs and the

crystal oscillator are stopped.

11

VDD48

PWR

Power pin for the 48MHz output.3.3V

12

FSLA/USB_48MHz

I/O

3.3V tolerant input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock

output. 3.3V.

13

GND

PWR

Ground pin.

14

DOTT_96MHz

OUT

True clock of differential pair for 96.00MHz DOT clock.

15

DOTC_96MHz

OUT

Complement clock of differential pair for 96.00MHz DOT clock.

16

FSLB/TEST_MODE

IN

3.3V tolerant input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time

input to select between Hi-Z and REF/N divider mode while in test mode.

Refer to Test Clarification Table.

17

LCDCLK_SST/SRCCLKT0

OUT

True clock of LCDCLK_SS output / True clock of SRCCLK differential pair.

Selected by SEL_LCDCLK#

18

LCDCLK_SSC/SRCCLKC0

OUT

Complementary clock of LCDCLK_SS output / Complementary clock of

SRCCLK differential pair. Selected by SEL_LCDCLK#

19

SRCCLKT1

OUT

True clock of differential SRC clock pair.

20

SRCCLKC1

OUT

Complement clock of differential SRC clock pair.

21

VDDSRC

PWR

Supply for SRC clocks, 3.3V nominal

22

SRCCLKT2

OUT

True clock of differential SRC clock pair.

23

SRCCLKC2

OUT

Complement clock of differential SRC clock pair.

24

SRCCLKT3

OUT

True clock of differential SRC clock pair.

25

SRCCLKC3

OUT

Complement clock of differential SRC clock pair.

26

SRCCLKT4_SATA

OUT

True clock of differential SRC/SATA pair.

27

SRCCLKC4_SATA

OUT

Complement clock of differential SRC/SATA pair.

28

VDDSRC

PWR

Supply for SRC clocks, 3.3V nominal