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SSD1818A bảng dữ liệu(PDF) 21 Page - List of Unclassifed Manufacturers |
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SSD1818A bảng dữ liệu(HTML) 21 Page - List of Unclassifed Manufacturers |
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21 / 47 page ![]() SSD1818A Rev 1.2 P 21/47 Mar 2004 Solomon Systech Reset Circuit This block includes Power On Reset (POR) circuitry and the hardware reset pin, RES . The POR and Hardware reset performs the same reset function. Once RES receives a reset pulse, all internal circuitry will start to initialize. Minimum pulse width the reset sequence is 5 - 10us. Status of the chip after reset is given by: Display is turned OFF Default Display Mode: 104 x 64 + 1 Icon Line Normal segment and display data column address mapping (Seg0 mapped to Row address 00h) Read-modify-write mode is OFF Power control register is set to 000b Shift register data clear in serial interface Bias ratio is set to default: 1/9 Static indicator is turned OFF Display start line is set to GDDRAM column 0 Column address counter is set to 00h Page address is set to 0 Normal scan direction of the COM outputs Contrast control register is set to 20h Test mode is turned OFF Temperature Coefficient is set to TC0 Note: Please find more explanation in the Applications Note attached at the back of the specification. Display Data Latch This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level. 64 MUX: 104 + 65 = 169 HV Buffer Cell (Level Shifter) HV Buffer Cell works as a level shifter, which translates the low voltage output signal to the required driving voltage. The output is shifted out with reference an internal FRM clock that comes from the Display Timing Generator. The level selector, which is synchronized with the internal M signal, gives the voltage levels. Level Selector Level Selector is a control of the display synchronization. Display voltage levels can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform. |
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