ADF4371 datasheet(24/46 Pages) AD

24 / 46 page

ADF4371

Preliminary Technical Data

Rev. PrI | Page 24 of 46

Address: 0x12, Reset: 0x40, Name: REG0012

Table 18. Bit Descriptions for REG0012

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

EN_AUTOCAL

Enables Autocal

0x1

R/W

0: VCO Autocal Disabled.

1: VCO Autocal Enabled.

PRE_SEL

Prescaler Select. The dual-modulus prescaler is set by this bit. The Prescaler, at the input to

the N divider, divides down the RFin signal so the N divider can handle it. The prescaler

setting affects the RF frequency and the minimum and maximum INT value.

0x0

R/W

0: 4/5 Prescaler.

1: 8/9 Prescaler.

[4:0]

RESERVED

Reserved.

0x0

Address: 0x14, Reset: 0x00, Name: REG0014

Table 19. Bit Descriptions for REG0014

Bits

Bit Name

Description

Reset

Access

[7:0]

FRAC1WORD[7:0]

25-Bit FRAC1 Value. Sets the FRAC1 value

0x0

R/W

Address: 0x15, Reset: 0x00, Name: REG0015

Table 20. Bit Descriptions for REG0015

Bits

Bit Name

Description

Reset

Access

[7:0]

FRAC1WORD[15:8]

25-Bit FRAC1 Value. Sets the FRAC1 value

0x0

R/W

Address: 0x16, Reset: 0x00, Name: REG0016

Table 21. Bit Descriptions for REG0016

Bits

Bit Name

Description

Reset

Access

[7:0]

FRAC1WORD[23:16]

25-Bit FRAC1 Value. Sets the FRAC1 value

0x0

R/W

Address: 0x17, Reset: 0x00, Name: REG0017

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