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STV9936S bảng dữ liệu(PDF) 39 Page - STMicroelectronics |
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STV9936S bảng dữ liệu(HTML) 39 Page - STMicroelectronics |
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39 / 48 page ![]() 39/48 STV9936P/S Application Hints 9.2 Hardware Hints q The serial resistors on the ROUT, GOUT, BOUT and FBLK outputs must be as close as possible to the device. q Both decoupling capacitors (100 nF and 100 µF) must be as close as possible to the analog (pin 13) and digital (pin5) power supplies (see Figure 14). q PLL network must be close to the device but far from the ROUT, GOUT, BOUT and FBLK outputs. PLL network and ROUT, GOUT, BOUT and FBLK outputs should be separated by the AVDD 3.3 V power trace (see Figure 15 and Figure 16). q PLL ground (AGND) should not be connected either to DVSS or to other grounds of the videoboard, as the ground is already connected internally (see Figure 15 and Figure 16). |
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