HT46C63 datasheet(10/44 Pages) HOLTEK

10 / 44 page

HT46R63/HT46C63

Rev. 1.90

May 17, 2004

cessible. At a subroutine call or interrupt

acknowledgment, the contents of the program counter

are pushed onto the stack. At the end of a subroutine or

an interrupt routine, signaled by a return instruction

(RET or RETI), the program counter is restored to its

previous value from the stack. After a chip reset, the

stack pointer will point to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decreased (by RET or RETI), the interrupt will

be serviced. This feature prevents stack overflow allow-

ing the programmer to use the structure more easily. In

similar case, if the stack is full and a

²call² is subse-

quently executed, stack overflow occurs and the first en-

try will be lost (only the most recent 8 return addresses

are stored).

Data Memory

- RAM

The data memory is designed with 239

´8 bits. The

data memory is divided into two functional groups: spe-

cial function registers and general purpose data mem-

ory (208

´8). Most are read/write, but some are read

only.

The special function registers include the indirect ad-

dressing register 0 and 1 (R0;00H, R1;02H), memory

pointer 0 and 1 (MP0;01H, MP1;03H), bank pointer

(BP:04H), accumulator (ACC;05H), program counter

lower-order byte register (PCL;06H), table pointer

(TBLP;07H), table higher-order byte register

(TBLH;08H), real time clock control register

(RTCC;09H), status register (STATUS;0AH), interrupt

control register (INTC0;0BH), timer higher-order byte

(TMRL;0DH), timer control register (TMRC;0EH), I/O

port data registers (PA;12H, PB;14H, PC;16H, PD;18H),

I/O port control registers (PAC;13H, PBC;15H,

PCC;17H, PDC;19H), PWM0 (1AH), PWM1 (1BH),

PWM2 (1CH), PWM3 (1DH), INTC1 (1EH),the A/D re-

sult register (ADR;21H), the A/D control register

(ADCR;22H) and the A/D clock setting register

(ACSR;23H). The remaining space before the 30H is re-

served for future expansion and reading these locations

will return the result

²00H². The general-purpose data

memory, addressed from 30H to FFH, is used for data

and control information under instruction commands.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and cleared by

²SET [m].i² and

²CLR [m].i², respectively. They are also indirectly acces-

sible through memory pointers (MP0 and MP1).

Indirect Addressing Register

Location 00H (02H) is indirect addressing registers that

are not physically implemented. Any read/write opera-

tion of [00H] ([02H]) will access data memory pointed to

by MP0 (MP1). Reading location 00H (02H) itself indi-

rectly will return the result

²00H². Writing indirectly re-

sults in no operation.

The memory pointers are 8-bit registers. Only the

MP1/R1 can be used to access the LCD RAM (BP=1).

S p e c i a l P u r p o s e

D A T A M E M O R Y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

: U n u s e d

R e a d a s " 0 0 "

G e n e r a l P u r p o s e

D a t a M e m o r y

( 2 0 8 B y t e s )

F F H

2 0 H

2 1 H

2 2 H

2 3 H

2 4 H

2 F H

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M P 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M P 1

B P

A C C

P C L

T B L P

T B L H

R T C C

S T A T U S

I N T C 0

T M R H

T M R L

T M R C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P W M 0

P W M 1

P W M 2

P W M 3

I N T C 1

A D R

A D C R

A C S R

3 0 H

RAM Mapping

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