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AD9520-1/PCBZ bảng dữ liệu(PDF) 18 Page - Analog Devices |
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AD9520-1/PCBZ bảng dữ liệu(HTML) 18 Page - Analog Devices |
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18 / 80 page ![]() AD9520-1 Data Sheet Rev. B | Page 18 of 80 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND. PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VS REFMON LD VCP CP STATUS REF_SEL SYNC LF BYPASS VS VS CLK CLK CS SCLK/SCL OUT3 (OUT3A) OUT3 (OUT3B) VS_DRV OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) VS VS OUT8 (OUT8B) OUT8 (OUT8A) OUT7 (OUT7B) OUT7 (OUT7A) VS_DRV OUT6 (OUT6B) OUT6 (OUT6A) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9520 TOP VIEW (Not to Scale) Figure 5. Pin Configuration Table 21. Pin Function Descriptions Pin No. Input/ Output Pin Type Mnemonic Description 1, 11, 12, 32, 40, 41, 49, 57, 60, 61 I Power VS 3.3 V Power Pins. 2 O 3.3 V CMOS REFMON Reference Monitor (Output). This pin has multiple selectable outputs. 3 O 3.3 V CMOS LD Lock Detect (Output). This pin has multiple selectable outputs. 4 I Power VCP Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.25 V. VCP must still be connected to 3.3 V if the PLL is not used. 5 O Loop filter CP Charge Pump (Output). This pin connects to an external loop filter; it can be left unconnected if the PLL is not used. 6 O 3.3 V CMOS STATUS Programmable Status Output. 7 I 3.3 V CMOS REF_SEL Reference Select. This pin selects REF1 (low) or REF2 (high) and has an internal 30 kΩ pull-down resistor. 8 I 3.3 V CMOS SYNC Manual Synchronization and Manual Holdover. This pin initiates a manual synchronization and is used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor. 9 I Loop filter LF Loop Filter (Input). This pin connects internally to the VCO control voltage node. 10 O Loop filter BYPASS This pin is for bypassing the LDO to ground with a 220 nF capacitor. It can be left unconnected if the PLL is not used. 13 I Differential clock input CLK Along with CLK, this pin is the differential input for the clock distribution section. 14 I Differential clock input CLK Along with CLK, this pin is the differential input for the clock distribution section. If a single-ended input is connected to the CLK pin, connect a 0.1 μF bypass capacitor from this pin to ground. |
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