AD9520-1SLASHPCBZ datasheet(67/80 Pages) AD

67 / 80 page

Data Sheet

AD9520-1

Rev. B | Page 67 of 80

Reg.

Addr.

(Hex)

Bits Name

Description

[1:0] Antibacklash

pulse width

Bit

Antibacklash Pulse Width (ns)

2.9 (default)

1.3

6.0

2.9

0x018 7

Enable CMOS

reference input

dc offset

Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost.

0: disables dc offset (default).

1: enables dc offset.

[6:5] Lock detect

counter

Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked

condition.

Bit

PFD Cycles to Determine Lock

5 (default)

255

Digital lock

detect window

If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock detect

flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.

0: high range (default). The default setting is 3.5 ns.

1: low range.

Disable digital

lock detect

Digital lock detect operation.

0: normal lock detect operation (default).

1: disables lock detect.

[2:1] VCO calibration

divider

Divider used to generate the VCO calibration clock from the PLL reference clock (see the VCO Calibration section for the

recommended setting of the VCO calibration divider based on the PFD rate).

Bit

VCO Calibration Clock Divider

2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R.

4. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R.

8. This setting is fine for PFD frequencies < 50 MHz.

16 (default). This setting is fine for any PFD frequency, but it also results in the longest VCO calibration time.

VCO calibration

now

Initiates VCO calibration. This bit must be toggled from 0b to 1b in the active registers. The sequence to initiate a calibration

is as follows: program to 0b, followed by an IO_UPDATE (Register 0x232[0]); then program to 1b, followed by another

IO_UPDATE (Register 0x232[0]). This sequence gives complete control over when the VCO calibration occurs relative to the

programming of other registers that can impact the calibration (default = 0b). Note that the VCO divider (Register 0x1E0[2:0]) must

not be static during VCO calibration.

0x019 [7:6] R, A, B counters

SYNC pin reset

Bit

Action

Does nothing on SYNC (default).

Asynchronous reset.

Synchronous reset.

Does nothing on SYNC.

[5:3] R path delay

R path delay, see Table 2 (default: 0x0).

[2:0] N path delay

N path delay, see Table 2 (default: 0x0).

0x01A 7

Enable STATUS

pin divider

Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the

R and N dividers.

0: divide-by-4 disabled on STATUS pin (default).

1: divide-by-4 enabled on STATUS pin.

Ref freq

monitor

threshold

Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO frequency monitor’s

detection threshold (see Table 17: REF1, REF2, and VCO frequency status monitor parameter).

0: frequency valid if frequency is above 1.02 MHz (default).

1: frequency valid if frequency is above 6 kHz.

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