MLX71120

300 to 930MHz

FSK/FM/ASK Receiver

REVISION 009 - JUNE 16, 2017

3901071120

1.9. Reference Oscillator

A Colpitts crystal oscillator with integrated functional capacitors is used as the reference oscillator (RO) of the PLL

synthesizer. The equivalent input capacitance CRO offered to the crystal at pin ROI is about 18pF. The crystal oscillator

features an amplitude control loop. This is to assure a very stable frequency over the specified supply voltage and

temperature range together with a short start-up time. A buffer amplifier with hysteresis is between RO and PFD. Also

a clock divider follows the buffer.

1.10. Clock Output

The clock output pin CKOUT is an open-drain output. For power saving reasons, the circuit is only active if an external

pull-up resistor RCL is applied to the pin. Furthermore, RCL can be used to adjust the clock waveform. It forms an RC

low-pass together with the capacitive load at the pin, the parasitics of the PCB and the input capacitance of the

external circuitry (e.g. a microcontroller).

The clock output feature is disabled if pin CKOUT is connected to ground or left open.

Fig. 3: Clock output implementation

1.11. FSK Demodulator

The integrated FSK demodulator is based on a phase-coincidence demodulator principle. An injection-locked oscillator

(ILO) is used as a frequency-dependent phase shifter. This topology features a good linearity of the frequency-phase

relationship over the entire locking range. The type of demodulator has no built-in constraints regarding the

modulation index. It also offers a wide carrier acceptance range.

In addition, the demodulator provides an AFC loop for correcting the remaining free-running frequency error and drift

effects, and also to remove possible frequency offsets between transmitter and receiver frequencies. The AFC loop

features a dead band which means that the AFC loop is only closed if the demodulator output voltage leaves the linear

region of the demodulator. Most of the time, the control loop is open. This leads to several advantages. The AFC loop

bandwidth can be high and therefore the reaction time is short. Furthermore the demodulator itself has no low-end

cut-off frequency.

The FSK demodulator has a negative control slope, this means the output voltage decreases by increasing the IF2

frequency. This guarantees an overall positive slope because the mixer section converts the receive frequency to IF2

either with high-low or low-high side injection.

The FSK demodulator is turned off during ASK demodulation.

CLKO

DIV8

Control

logic

RO

output

RCL

VCC