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ADCLK905BCPZ-R2 bảng dữ liệu(PDF) 7 Page - Analog Devices |
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ADCLK905BCPZ-R2 bảng dữ liệu(HTML) 7 Page - Analog Devices |
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7 / 16 page ![]() Data Sheet ADCLK905/ADCLK907/ADCLK925 Rev. B | Page 7 of 16 D1 D1 D2 D2 Q1 Q1 Q2 Q2 12 11 10 1 3 4 9 2 ADCLK907 TOP VIEW (Not to Scale) NOTES 1. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT. IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED THERMAL AND/OR MECHANICAL STABILITY IS DESIRED. EXPOSED METAL AT THE CORNERS OF THE PACKAGE IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLEARANCE TO VIAS AND OTHER COMPONENTS. Figure 5. ADCLK907 Pin Configuration Table 5. Pin Function Descriptions for Dual 1:1 ADCLK907 Buffer Pin No. Mnemonic Description 1 D1 Noninverting Input 1. 2 D1 Inverting Input 1. 3 D2 Noninverting Input 2. 4 D2 Inverting Input 2. 5 VT2 Center Tap 2. Center tap of 100 Ω input resistor, Channel 2. 6 VREF2 Reference Voltage 2. Reference voltage for biasing ac-coupled inputs, Channel 2. 7, 14 VEE Negative Supply Voltage. 8, 13 VCC Positive Supply Voltage. Pin 8 and Pin 13 are not strapped internally. 9 Q2 Inverting Output 2. 10 Q2 Noninverting Output 2. 11 Q1 Inverting Output 1. 12 Q1 Noninverting Output 1. 15 VREF1 Reference Voltage 1. Reference voltage for biasing ac-coupled inputs, Channel 1. 16 VT1 Center Tap 1. Center tap of 100 Ω input resistor, Channel 1. EPAD Exposed Pad. The exposed pad is not electrically connected to any part of the circuit. It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components. |
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