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WM9714CLGEFL/V bảng dữ liệu(PDF) 80 Page - Cirrus Logic |
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WM9714CLGEFL/V bảng dữ liệu(HTML) 80 Page - Cirrus Logic |
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80 / 120 page  WM9714L 80 Rev 4.0 REGISTER MAP Reg Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default Reset 0 SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 6174h Speaker Volume MUL ZCL MUR ZCR 8080h Headphone Volume MUL ZCL MUR ZCR 8080h OUT3/4 Volume MU4 ZC4 MU3 ZC3 8080h MONO Vol & MONOIN PGA Vol / Routing M2H M2S 0 MU ZC C880h LINEIN PGA Volume / Routing L2H L2S L2M 0 0 0 E808h DAC PGA Volume / Routing D2H D2S D2M 0 0 0 E808h MIC PGA Volume 0 0 0 0 0 0 0808h MIC Routing 0 0 0 0 0 0 0 0 MA2M MB2M MIC2MB ST 00DAh Record PGA Volume RMU GRL ZC GRR 8000h Record Routing / Mux Select R2M BST 0 REC BST D600h PCBEEP Volume / Routing B2H B2S B2M 0 0 0 0 AAA0h VxDAC Volume / Routing V2H V2S V2M 0 0 0 0 AAA0h AUXDAC Volume / Routing A2H A2S A2M 0 0 0 0 AAA0h Output PGA Mux Select 0000h DAC 3D Control & INV Mux Select 0 0 0 0 3DLC 3DUC 0000h DAC Tone Control BB 0 0 BC 0 DAT 0 TC 0F0Fh MIC Input Select & Bias / Detect Ctrl MBOP2E N MBOP1E N MBVOL 0040h Output Volume Mapping (Jack Insert) 0 0 0 0 0 0 0 0 0 0 0 JIEN 0000h Powerdown Ctrl/Stat 0 PR6 PR5 PR4 PR3 PR2 PR1 PR0 0 0 0 0 REF ANL DAC ADC 7F00h Extended Audio ID ID1 ID0 0 0 REV1 REV0 AMAP LDAC SDAC CDAC 0 0 VRM SPDIF DRA VRA 0405h Ext'd Audio Stat/Ctrl 0 0 0 0 0 SPCV 0 0 0 0 0 SEN 0 VRA 0410h Audio DACs Sample Rate BB80h AUXDAC Sample Rate BB80h Audio ADCs Sample Rate BB80h PCM codec control CTRL 0 VDACO SR CP FSP 4523h SPDIF control V DRS L PRE COPY AUD IB PRO 2000h Powerdown (1) PADCPD VMID 1M TSHUT VXDAC AUXDAC VREF PLL 1 DACL DACR ADCL ADCR HPLX HPRX SPKX MX FDFFh Powerdown (2) MCD MIC BIAS MONO OUT4 OUT3 HPL HPR SPKL SPKR LL LR MOIN MA MB MPA MPB FFFFh General Purpose 0 0 3DE 0 0 0 0 0 LB 0 0 0 0 0 0 0 0000h Fast Power-Up Control 0 0 0 0 0 0 0 0 0 MONO SPKL SPKR HPL HPR OUT3 OUT4 0000h MCLK / PLL Control 0 CLKSRC 0 CLKBX2 CLKAX2 CLKMUX 0080h MCLK / PLL Control LF SDM DIVSEL DIVCTL 0 0000h GPIO Pin Configuration 1 1 1 1 1 1 1 GC8 GC7 GC6 GC5 GC4 GC3 GC2 GC1 0 FFFEh GPIO Pin Polarity / Type C1P C2P PP AP TP SP MP GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 1 FFFFh GPIO Pin Sticky C1S C2S PS AS TS SS MS GS8 GS7 GS6 GS5 GS4 GS3 GS2 GS1 0 0000h GPIO Pin Wake-Up C1W C2W PW AW TW SW MW GW8 GW7 GW6 GW5 GW4 GW3 GW2 GW1 0 0000h GPIO Pin Status C1I C2I PI AI TI SI MI GI8 GI7 GI6 GI5 GI4 GI3 GI2 GI1 0 GPIO pins GPIO Pin Sharing 1 1 1 1 1 1 1 GE8 0 GE6 GE5 GE4 0 GE2 1 0 FFFEh GPIO Pull UP/DOWN Ctrl PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 4000h Additional Functions (1) 0 0 0 0 RSTDIS WAKEE N IRQ INV 0000h Additional Functions (2) AMUTE C1 REF C2 REF 0 AMEN ADCO HPF 0 0000h ALC Control B032h ALC / Noise Gate Control 0 NGAT 0 NGG 3E00h AUXDAC input control XSLE 0000h Digitiser Reg 1 0 0 0 0 0 0 POLL CTC 0 0000h Digitiser Reg 2 0 0 0 0 0 0 SLEN 0006h Digitiser Reg 3 0 0 0 0 WAIT 0 0 0 0 0 0 1 0001h Digitiser Read Back 0 0000h Vendor ID1 574Dh Vendor ID2 4C13h PENDIV DCDRVSEL EARSPKSEL MODE DIV SEL WL FMT SPSR CC (Category Code) AUXDACSLT AUXDAC VAL ADCSEL 7Ah ADCSRC ADCD (AUXADC DATA) DEL SLT 7Eh ASCII character “L” Device Identifier 7Ch 78h PRP MSK ASCII character “W” ASCII character “M” 74h 76h CR 64h ASS 60h 62h ALCSEL MAXGAIN ZCTIMEOUT NGTH (threshold) ALCL (target level) HLD (hold time) 5Ch C1SRC C2SRC VBIAS 58h 5Ah COMP2DEL Die Revision HPMODE JSEL 50h 52h 54h 56h 4Ch 4Eh 40h 42h 44h 46h 3Ch 3Eh 36h 3Ah 2Eh AUXDACSR (Auxiliary DAC Sample Rate) 32h ADCSR (Audio ADCs Sample Rate) 2Ah SPSA 2Ch DACSR (Audio DACs Sample Rate) 24h 26h DCY (decay time) ATK (attack time) N[3:0] PGADDR PGDATA SEXT[6:4] SEXT[3:0] 28h 20h BASS TRBL 22h MICCMPSEL MPASEL MPABST MPBBST MCDTHR MCDSCTHR 1Eh INVA INVB 3DDEPTH HPL HPR OUT3 OUT4 1Ch MONO SPKL SPKR 1Ah A2HVOL A2SVOL A2MVOL 18h V2HVOL V2SVOL V2MVOL RECSL RECSR 16h B2HVOL B2SVOL B2MVOL 14h R2H R2HVOL R2M 10h MIC2H MIC2HVOL 12h (Extended) RECVOLL (Extended) RECVOLR 0Ch DACLVOL DACRVOL 0Eh MICAVOL MICBVOL 08h MONOINVOL MONOVOL 0Ah LINELVOL LINERVOL 06h OUT4VOL OUT3VOL 04h HPLVOL HPRVOL 00h 02h SPKLVOL SPKRVOL Table 63 WM9714L Register Map Note: Register 46h provides access to a sub-page address system to set the SPLL[6:0] and K[21:0] register bits (see Table 6). |
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