LOW SKEW, 1-TO-16

DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

8516 DATA SHEET

4

REVISION B 6/11/15

A

A

A

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

DD

Positive Supply Voltage

3.135

3.3

3.465

V

I

DD

Static Power Supply Current

RL = 100

Ω

135

165

mA

No Load

60

75

mA

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

I

IH

Input High Current

CLK

V

150

µA

nCLK

V

5

µA

I

IL

Input Low Current

CLK

V

-5

µA

nCLK

V

-150

µA

V

PP

Peak-to-Peak Voltage

0.15

1.3

V

V

CMR

Common Mode Input Voltage;

NOTE 1, 2

GND + 0.5

V

V

NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V

NOTE 2: Common mode voltage is defined ast V

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

IH

Input High Voltage

OE1, OE2

2

V

V

V

IL

Input Low Voltage

OE1, OE2

-0.3

0.8

V

I

IH

Input High Current

OE1, OE2

V

5

µA

I

IL

Input Low Current

OE1, OE2

V

-150

µA

Supply Voltage, V

DD

4.6V

Inputs, V

I

-0.5V to V

Outputs, V

O

-0.5V to V

Package Thermal Impedance,

θ

JA

47.9°C/W (0 lfpm)

Storage Temperature, T

STG

-65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device.These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions

beyond those listed in the DC Characteristics or AC Charac-

teristics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.