SSM2603 datasheet(17/31 Pages) AD

17 / 31 page

Data Sheet

SSM2603

Rev. D | Page 17 of 31

SOFTWARE CONTROL INTERFACE

The software control interface provides access to the user-selectable

control registers and can operate with a 2-wire (I2C) interface.

Within each control register is a control data-word consisting of

16 bits, MSB first. Bit B15 to Bit B9 are the register map address,

and Bit B8 to Bit B0 are register data for the associated register map.

SDIN generates the serial control data-word, SCLK clocks the

serial data, and CSB determines the I2C device address. If the

CSB pin is set to 0, the address selected is 0011010; if 1, the

address is 0011011.

CONTROL REGISTER SEQUENCING

1. Enable all of the necessary power management bits of

out bit should be set to 1 until the final step of the control

2. After the power management bits are set, program all other

necessary registers, with the exception of the active bit

[Register R9, Bit D0] and the out bit of the power manage-

ment register.

3. As described in the Digital Core Clock section of the

Theory of Operation, insert enough delay time to charge

the VMID decoupling capacitor before setting the active

bit [Register R9, Bit D0] .

4. Finally, to enable the DAC output path of the SSM2603, set

the out bit of Register R6 to 0.

1 TO 7

SDIN

SCLK

START

ADDR

R/W

ACK

SUBADDRESS

ACK

STOP

DATA

Figure 28. 2-Wire I2C Generalized Clocking Diagram

WRITE

SEQUENCE

READ

SEQUENCE

A(S)

B15

...

A(S)

...

A(M)

...

DEVICE

ADDRESS

DEVICE

ADDRESS

A(S)

B15

...

DEVICE

ADDRESS

DATA

(SLAVE DRIVE)

DATA

S/P = START/STOP BIT.

A0 = I2C R/W BIT.

A(S) = ACKNOWLEDGE BY SLAVE.

A(M) = ACKNOWLEDGE BY MASTER.

A(M) = ACKNOWLEDGE BY MASTER (INVERSION).

Figure 29. I2C Write and Read Sequences

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