SSM2603 datasheet(6/31 Pages) AD

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SSM2603

Data Sheet

Rev. D | Page 6 of 31

Table 5. Digital Audio Interface Master Mode Timing

Limit

Parameter

tMIN

tMAX

Unit

Description

tDST

PBDAT setup time to BCLK rising edge

tDHT

PBDAT hold time to BCLK rising edge

tDL

RECLRC/PBLRC propagation delay from BCLK falling edge

tDDA

RECDAT propagation delay from BCLK falling edge

tBCLKR

BCLK rising time (10 pF load)

tBCLKF

BCLK falling time (10 pF load)

tBCLKDS

45:55:00

55:45:00

BCLK duty cycle (normal and USB mode)

BCLK

PBLRC/

RECLRC

PBDAT

RECDAT

tDDA

tDST

tDHT

tDL

Figure 4. Digital Audio Interface Master Mode Timing

Table 6. Master Clock Timing1

Limit

Parameter

tMIN

tMAX

Unit

Description

tXTIY

MCLK/XTI clock cycle time

tMCLKDS

40:60

60:40

MCLK/XTI duty cycle

tXTIH

MCLK/XTI clock pulse width high

tXTIL

MCLK/XTI clock pulse width low

tCOP

CLKOUT propagation delay from MCLK/XTI falling edge

tCOPDIV2

CLKODIV2 propagation delay from MCLK/XTI falling edge

1 CLKDIV2 bit (Register R8, Bit D6) is set to 0.

tCOPDIV2

tCOP

MCLK/XTI

CLKOUT

CLKODIV2

tXTIH

tXTIL

tXTIY

Figure 5. System (MCLK) Clock Timing

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