SCF5250 datasheet(5/48 Pages) MOTOROLA

5 / 48 page

Introduction

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

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Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.

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Third-layer error encoding needs to be done in software. This can use approximately 5-10 Mhz of

performance for single-speed.

1.2.13 Dual UART Module

Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats

can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte

receive buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also

provides several error-detection and maskable-interrupt capabilities. Modem support includes

request-to-send (RTS) and clear-to-send (CTS) lines.

The system clock provides the clocking function from a programmable prescaler. You can select full

duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs

can interrupt the CPU on various normal or error-condition events.

1.2.14 Queued Serial Peripheral Interface QSPI

The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to

16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to

15 Mbits/second are possible at a CPU clock of 120 MHz. The QSPI supports master mode operation only.

1.2.15 Timer Module

The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer.

Timer0 has an external pin TOUT0, which can be used in Output Compare mode. This mode triggers an

external signal or interrupts the CPU when the timer reaches a set value, and can also generate waveforms

on TOUT0.

The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is

derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock (CPU clock

/ 2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs.

1.2.16 IDE and SmartMedia Interfaces

The SCF5250 system bus allows connection of an IDE hard disk drive or SmartMedia flash card with a

minimum of external hardware. The external hardware consists of bus buffers for address and data and are

intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the IDE

bus. The control signals for the buffers are generated in the SCF5250.

1.2.17 Analog/Digital Converter (ADC)

The six channel ADC is a based on the Sigma-Delta concept with 12-bit resolution. Both the analogue

comparator and digital sections of the ADC are provided internally. An external integrator circuit

(resistor/capacitor) is required, which is driven by the ADC output. A software interrupt is provided when

the ADC measurement cycle is complete.

SCF5250 bảng dữ liệu(PDF) 5 Page - Motorola, Inc