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SCF5250 bảng dữ liệu(PDF) 33 Page - Motorola, Inc |
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SCF5250 bảng dữ liệu(HTML) 33 Page - Motorola, Inc |
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33 / 48 page ![]() Electrical Characteristics SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1 Freescale Semiconductor 33 Figure 8. I2C Timing Definition Table 27. I2C Output Bus Timings Num Characteristic 96 MHz Units Min Max M103 SCL, SDA Valid to BCLK (input setup) 2 — nSec M11 BCLK to SCL, SDA Invalid (input hold) 4.5 — nSec M121 BCLK to SCL, SDA Low (output valid) — 10 nSec M132 BCLK to SCL, SDA Invalid (output hold) 3 — nSec 1. Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL or SDA are driven low by the processor. The time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values. 2. Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL or SDA are actively being driven or held low by the processor. 3. SCL and SDA are internally synchronized.This setup time must be met only if recognition on a particular clock is required. M2 M6 M1 M4 M7 M8 M9 M5 M3 SCL SDA |
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