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ICS950901 bảng dữ liệu(PDF) 11 Page - Integrated Circuit Systems |
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ICS950901 bảng dữ liệu(HTML) 11 Page - Integrated Circuit Systems |
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11 / 20 page ![]() 11 Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950901 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters. TA = 0 - 70C; Supply Voltage VDD = 3.3 V + - 5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage Vih 2VDD+0.3 V Input Low Voltage Vil VSS-0.3 0.8 V Input High Current Iih Vin = VDD -5 5 mA Input Low Current Iil1 Vin = 0 V; Inputs with no pull-up resistors -5 mA Input Low Current IIL2 Vin = 0 V; Inputs with no pull-up resistors -200 mA Operating IDD3.3OP Cl = 0 pF; Select @ 66M 100 mA Supply Current Cl = Full load @ 133.3 MHz 181 280 mA Power Down IREF=2.32mA 13 20 mA Supply Current IDD3.3PD IREF= 5mA 37 mA Input frequency Fi VDD = 3.3 V; MHz Pin Inductance Lpin 7nH CIN Logic Inputs 5 pF Input Capacitance1 Cout Output pin capacitance 6 pF CINX X1 & X2 pins 27 45 pF Transition Time1 Ttrans To 1st crossing of target Freq. 3 ms Settling Time1 Ts From 1st crossing to 1% target Freq. 3 ms Clk Stabilization1 TSTAB From VDD = 3.3V to 1% target Freq. 3 ms tPZH,tPZH output enable delay (all outputs) 1 10 ns tPLZ,tPZH output disable delay (all outputs) 1 10 ns 1 Guarenteed by design, not 100% tested in production. Delay |
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