Document Number: 002-14815 Rev. *D

Page 21 of 49

PRELIMINARY

CYW20719

b. During power-on reset, all inputs are disabled.

c. P15 and P37 should not be driven high externally while the part is held in reset (they can be floating or driven low). Failure to do so may cause some current to flow

through these pins until the part comes out of reset.

Table 6. GPIO Supermux Input Functions

Input

Description

SWDCK

Serial Wire Debugger Clock

SWDIO

Serial Wire Debugger I/O

spiffy1_clk[s]

SPIFFY 1 Clock (Slave)

spiffy1_cs[s]

SPIFFY 1 Chip Select (Slave)

spiffy1_mosi[s]

SPIFFY 1 MOSI (Slave)

spiffy1_miso[m]

SPIFFY 1 MISO (Master)

spiffy1_io2

SPIFFY 1 I/O 2 (Quad SPI)

spiffy1_io3

SPIFFY 1 I/O 3 (Quad SPI)

spiffy1_int[s]

SPIFFY 1 Interrupt (Slave)

spiffy2_clk[s]

SPIFFY 2 Clock (Slave)

spiffy2_cs[s]

SPIFFY 2 Chip Select (Slave)

spiffy2_mosi[s]

SPIFFY 2 MOSI (Slave)

spiffy2_miso[m]

SPIFFY 2 MISO (Master)

spiffy2_io2

SPIFFY 2 I/O 2

spiffy2_io3

SPIFFY 2 I/O 3

spiffy2_int[s]

SPIFFY 2 Interrupt (Slave)

puart_rx

Peripheral UART RX

puart_cts_n

Peripheral UART CTS

SCL

I2C Clock

SDA

I2C Data

SCL2

I2C2 Clock

SDA2

I2C2 Data

PCM_IN

PCM Input

PCM_CLK

PCM Clock

PCM_SYNC

PCM Sync

I2S_DI

I2S Data Input

I2S_WS

I2S Word Select

I2S_CLK

I2S Clock

PDM_IN_Ch_1

PDM Input Channel 1

PDM_IN_Ch 2

PDM Input Channel 2

Table 6. GPIO Supermux Input Functions (Cont.)

Input

Description