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S0078-01

V

CC

V

EE

VT = V

CC

–

2V

CDCM7005

Driver

LVPECL

Receiver

Z

= 50

O

W

50W

50W

Z

= 50

O

W

Yx

Yx

SPI CONTROL INTERFACE

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 13. LVPECL Output Loading During Device Test

The serial interface of the CDCM7005 is a simple SPI-compatible interface for writing to the registers of the

device and consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. There are four 32-bit wide

registers, which can be addressed by the two LSBs of a transferred word (bit 0 and bit 1). Every transmitted word

must have 32 bits, starting with MSB first. Each word can be written separately. Bit 7, 8, 10, and Bit 12 to 31 of

Word 3 are reserved for factory test purposes and must be filled with zeros. The transfer is initiated with the

falling edge of CTRL_LE; as long as CTRL_LE is high, no data can be transferred. During CTRL_LE, low data

can be written. The data has to be applied at CTRL_DATA and has to be stable before the rising edge of

CTRL_CLK. The transmission is finished by a rising edge of CTRL_LE. With the rising edge of CTRL_LE, the

new word is asynchronously transferred to the internal register (e.g., N, M, P, ...). Each word has to be

separately transmitted by this procedure.

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