T48C893 datasheet(7/82 Pages) ATMEL

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Giải thích chi tiết về linh kiện	The multiple times programmable (MTP) version for the MARC4 ROM types

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T48C893

Rev. A4, 22-Jan-02

7 (82)

MARC4 Architecture

3.1

General Description

The MARC4 microcontroller consists of an advanced

stack-based, 4-bit CPU core and on-chip peripherals. The

CPU is based on the HARVARD architecture with

physically separate program memory (ROM) and data

memory

(RAM).

Three

independent

buses,

the

instruction bus, the memory bus and the I/O bus, are used

for parallel communication between ROM, RAM and

peripherals. This enhances program execution speed by

allowing both instruction prefetching, and a simultaneous

communication to the on-chip peripheral circuitry. The

extremely powerful integrated interrupt controller with

associated eight prioritized interrupt levels supports fast

and efficient processing of hardware events. The MARC4

is designed for the high-level programming language

qFORTH. The core includes both, an expression and a

return

stack.

This

architecture

enables

high-level

language programming without any loss of efficiency or

code density.

Instruction

decoder

CCR

TOS

ALU

RAM

Program

256 x 4-bit

MARC4 CORE

Clock

Reset

Sleep

Memory bus

I/O bus

Instruction

bus

Reset

System

clock

Interrupt

controller

On–chip peripheral modules

94 8973

memory

Figure 3. MARC4 core

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