SC68C752B datasheet(26/49 Pages) PHILIPS

26 / 49 page

SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

26 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Remark: The three error bits (parity, framing, break) may not be updated correctly in the

ﬁrst read of the LSR when the input clock (XTAL1) is running faster than 36 MHz.

However, the second read is always correct. It is strongly recommended that when using

this device with a clock faster than 36 MHz, that the LSR be read twice and only the

second read be used for decision making. All other bits in the LSR are correct on all

reads.

7.6 Modem Control Register (MCR)

The MCR controls the interface with the mode, data set, or peripheral device that is

emulating the modem. Table 15 shows Modem Control Register bit settings.

[1]

MCR[7:5] can only be modiﬁed when EFR[4] is set, that is, EFR[4] is a write enable.

Table 15:

Modem Control Register bits description

Bit

Symbol

Description

MCR[7] [1]

Clock select.

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

MCR[6] [1]

TCR and TLR enable.

logic 0 = no action.

logic 1 = enable access to the TCR and TLR registers

MCR[5] [1]

Xon Any.

logic 0 = disable Xon Any function

logic 1 = enable Xon Any function

MCR[4]

Enable loopback.

logic 0 = normal operating mode

logic 1 = Enable local Loopback mode (internal). In this mode the

MCR[3:0] signals are looped back into MSR[7:4] and the TX output is

looped back to the RX input internally.

MCR[3]

OPA/OPB control.

logic 0 = forces OPA/OPB output to HIGH state

logic 1 = forces OPA/OPB output to LOW state. In Loopback mode,

controls MSR[7].

MCR[2]

FIFO Ready enable.

logic 0 = Disable the FIFO Rdy register

logic 1 = Enable the FIFO Rdy register. In Loopback mode, controls

MSR[6].

MCR[1]

RTS

logic 0 = force RTS output to inactive (HIGH)

logic 1 = force RTS output to active (LOW). In Loopback mode, controls

MSR[4]. If Auto-RTS is enabled, the RTS output is controlled by

hardware ﬂow control.

MCR[0]

DTR

logic 0 = force DTR output to inactive (HIGH)

logic 1 = force DTR output to active (LOW). In Loopback mode, controls

MSR[5].

SC68C752B bảng dữ liệu(PDF) 26 Page - NXP Semiconductors

SC68C752B bảng dữ liệu(HTML) 26 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

bảng dữ liệu tải về

Link URL