SC68C752B datasheet(20/49 Pages) PHILIPS

20 / 49 page

SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

20 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Each register is selected using address lines A0, A1, A2, and in some cases, bits from

other registers. The programming combinations for register selection are shown in

Table 10.

[1]

MCR[7] can only be modiﬁed when EFR[4] is set.

[2]

Accessed by a combination of address pins and register bits.

[3]

Accessible only when LCR[7] is logic 1.

[4]

Accessible only when LCR is set to 1011 1111 (BFh).

[5]

Accessible only when EFR[4] = 1 and MCR[6] = 1, that is, EFR[4] and MCR[6] are read/write enables.

[6]

Accessible only when CS = 0, MCR[2] = 1, and loopback is disabled (MCR[4] = 0).

Fig 13. Crystal oscillator connections

002aaa870

47 pF

XTAL1

XTAL2

1.8432 MHz

22 pF

33 pF

XTAL1

XTAL2

1.5 k

Ω

1.8432 MHz

22 pF

Table 10:

Read mode

Write mode

Receive Holding Register (RHR)

Transmit Holding Register (THR)

Interrupt Enable Register (IER)

Interrupt Enable Register

Interrupt Identiﬁcation Register (IIR)

FIFO Control Register (FCR)

Line Control Register (LCR)

Line Control Register

Modem Control Register (MCR) [1]

Modem Control Register [1]

Line Status Register (LSR)

Modem Status Register (MSR)

ScratchPad Register (SPR)

ScratchPad Register

Divisor Latch LSB (DLL) [2] [3]

divisor latch LSB [2] [3]

Divisor Latch MSB (DLH) [2] [3]

divisor latch MSB [2] [3]

Enhanced Feature Register (EFR) [2] [4]

Enhanced Feature Register [2] [4]

Xon1 word [2] [4]

Xon2 word [2] [4]

Xoff1 word [2] [4]

Xoff2 word [2] [4]

Transmission Control Register (TCR) [2] [5] Transmission Control Register [2] [5]

Trigger Level Register (TLR) [2] [5]

Trigger Level Register [2] [5]

FIFO ready register [2] [6]

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