PC8260 datasheet(45/53 Pages) ATMEL

45 / 53 page

PC8260 PowerQUICC II

2131B–HIREL–02/03

Notes:

1. Input specifications are measured from TTL level (0.8 or 2.0V) of the signal to the 1.4

level of the rising edge of CLKIN.

2. Timings are measured at the pins.

Notes:

1. Output specifications are measured from the 1.4V level of the rising edge of CLKIN to

the TTL level (0.8 or 2.0V) of the signal.

2. Timings are measured at the pin.

Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC

timing. When data pipelining is activated, sp12 can be used for data bus setup even

when ECC or PARITY are used. Also, sp33a can be used as the AC specification for DP

signals.

Table 13. AC Characteristics for SIU Inputs

Spec_num

Characteristics

Setup (ns)

Hold (ns)

sp11/sp10

AACK/ARTRY/TA/TEA/DBG/BG/BR

sp12/sp10

Data Bus in Normal mode

sp13sp10

Data Bus in ECC and PARITY Modes

sp14/sp10

DP pins

sp15/sp10

All Other Pins

Table 14. AC Characteristics for SIU Outputs

Spec_num

Characteristics

Max Delay (ns)

Min Delay (ns)

sp31/sp30

PSDVAL/TEA/TA

sp32/sp30

ADD/ADD_atr./BADDR/CIGBL/WT

sp33a/sp30

Data Bus

sp33b/sp30

sp34/sp10

Memc Signals/ALE

sp35/sp10

All Other Signals

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