K6R1016C1C-C/C-L, K6R1016C1C-I/C-P

CMOS SRAM

Revision 4.0

- 6 -

September 2001

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

device.

5. Transition is measured

±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

Valid Data

High-Z

CS

Address

UB, LB

OE

Data out

50%

50%

Current

Address

CS

UB, LB

WE

Data in

Data out

High-Z

High-Z

Valid Data

OE