IMX6SLLCEC datasheet(9/90 Pages) NXP

9 / 90 page

Modules List

i.MX 6SLL Applications Processors for Consumer Products, Rev. 0.2, 11/2017

NXP Semiconductors

OCOTP_

CTRL

OTP

Controller

Security

The On-Chip OTP controller (OCOTP_CTRL) provides an interface for

reading, programming, and/or overriding identification and control information

stored in on-chip fuse elements. The module supports

electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also

provides a set of volatile software-accessible signals that can be used for

software control of hardware elements, not requiring non-volatility. The

OCOTP_CTRL provides the primary user-visible mechanism for interfacing

with on-chip fuse elements. Among the uses for the fuses are unique chip

identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,

boot characteristics, and various control signals, requiring permanent

non-volatility.

OCRAM

On-Chip Memory

Controller

Data Path

The On-Chip Memory controller (OCRAM) module is designed as an interface

between system’s AXI bus and internal (on-chip) SRAM memory module.

In i.MX 6SLL processor, the OCRAM is used for controlling the 128 KB

multimedia RAM through a 64-bit AXI bus.

OCRAM_L

On-Chip Memory

Controller for

L2 Cache

Data Path

The On-Chip Memory controller for L2 cache (OCRAM_L2) module is

designed as an interface between system’s AXI bus and internal (on-chip) L2

cache memory module during boot mode.

OSC 32

kHz

OSC 32 kHz

Clocking

Generates 32.768 kHz clock from external crystal.

PMU

Power-

Management

functions

Data Path

Integrated power management unit. Used to provide power to various SoC

domains.

PWM-1

PWM-2

PWM-3

PWM-4

Pulse Width

Modulation

Connectivity

Peripherals

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to

generate sound from stored sample audio images and it can also generate

tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound.

PXP

PiXel

Processing

Pipeline

Display

Peripherals

A high-performance pixel processor capable of 1 pixel/clock performance for

combined operations, such as color-space conversion, alpha blending,

gamma-mapping, and rotation. The PXP is enhanced with features

specifically for gray scale applications. In addition, the PXP supports

traditional pixel/frame processing paths for still-image and video processing

applications, allowing it to interface with either of the integrated EPD

controllers.

RAM

128 KB

Internal RAM

Internal

Memory

Internal RAM, which is accessed through OCRAM memory controller.

RNGB

Random Number

Generator

Security

Random number generating module.

ROM

96KB

Boot ROM

Internal

Memory

Supports secure and regular Boot Modes. Includes read protection on 4K

region for content protection.

ROMCP

ROM Controller

with Patch

Data Path

ROM Controller with ROM Patch support

SDMA

Smart Direct

Memory

Access

System

Control

Peripherals

The SDMA is multi-channel flexible DMA engine. It helps in maximizing

system performance by off-loading the various cores in dynamic data routing.

Table 2. i.MX 6SLL Modules List (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

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