ISL6563CRZ datasheet(16/20 Pages) RENESAS

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ISL6563

FN9126 Rev 8.00

Page 16 of 20

Jun 10, 2010

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

VMAX. This places an upper limit on inductance.

While the previous equation addresses the leading edge,

Equation 24 gives the upper limit on L for cases where the

trailing edge of the current transient causes a greater output

voltage deviation than the leading edge.

Normally, the trailing edge dictates the selection of L, since

duty cycles are usually less than 50%. Nevertheless, both

inequalities should be evaluated, and L should be selected

based on the lower of the two results. In all equations in this

paragraph, L is the per-channel inductance and C is the total

output bulk capacitance.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit

and lead to device overvoltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turnoff

transition of the upper PWM MOSFET. Prior to turnoff, the

upper MOSFET was carrying channel current. During the

turnoff, current stops flowing in the upper MOSFET and is

picked up by the lower MOSFET. Any inductance in the

switched current path generates a large voltage spike during

the switching interval. Careful component selection, tight

layout of the critical components, and short, wide circuit

traces minimize the magnitude of voltage spikes.

There are two sets of critical components in a DC-DC

converter using an ISL6563 controller. The power

components are the most critical because they switch large

amounts of energy. Next are small signal components that

connect to sensitive nodes or supply critical bypassing

current and signal coupling.

Note that as the ISL6563 does not allow external adjustment

of the channel-to-channel current balancing (current

information is multiplexed across a single RISEN resistor), it

is important to have a symmetrical layout, preferably with the

controller equidistantly located from the two power trains it

controls. Equally important are the gate drive lines (UGATE,

LGATE, PHASE): since they drive the power train MOSFETs

using short, high current pulses, it is important to size them

accordingly and reduce their overall impedance. Equidistant

placement of the controller to the two power trains also helps

keeping these traces equally long (equal impedances,

resulting in similar driving of both sets of MOSFETs).

The power components should be placed first. Locate the

input capacitors close to the power switches. Minimize the

length of the connections between the input capacitors, CIN,

and the power switches. Locate the output inductors and

output capacitors between the MOSFETs and the load.

Locate the high-frequency decoupling capacitors (ceramic)

as close as practicable to the decoupling target, making use

of the shortest connection paths to any internal planes, such

as vias to GND immediately next, or even onto the capacitor

solder pad.

The critical small components include the bypass capacitors

for VCC and PVCC. Locate the bypass capacitors, CBP,

close to the device. It is especially important to locate the

components associated with the feedback circuit close to

their respective controller pins, since they belong to a high-

impedance circuit loop, sensitive to EMI pick-up. It is

important to place the RISEN resistor close to the respective

terminal of the ISL6563.

A multi-layer printed circuit board is recommended. Figure 9

shows the connections of the critical components for one

output channel of the converter. Note that capacitors CxxIN

and CxxOUT could each represent numerous physical

capacitors. Dedicate one solid layer, usually the one

underneath the component side of the board, for a ground

plane and make all critical component ground connections

with vias to this layer. Dedicate another solid layer as a power

plane and break this plane into smaller islands of common

voltage levels. Keep the metal runs from the PHASE terminal

to inductor LOUT short. The power plane should support the

input power and output power nodes. Use copper filled

polygons on the top and bottom circuit layers for the phase

nodes. Use the remaining printed circuit layers for small signal

wiring. The wiring traces from the IC to the MOSFETs’ gates

and sources should be sized to carry at least one ampere of

current (0.02” to 0.05”).

Component Selection Guidelines

Output Capacitor Selection

The output capacitor is selected to meet both the dynamic

load requirements and the voltage ripple requirements. The

load transient a microprocessor impresses is characterized

by high slew rate (di/dt) current demands. In general,

multiple high quality capacitors of different size and dielectric

are paralleled to meet the design constraints.

Should the load be characterized by high slew rates, attention

should be particularly paid to the selection and placement of

high-frequency decoupling capacitors (MLCCs, typically

multi-layer ceramic capacitors). High frequency capacitors

supply the initially transient current and slow the load

rate-of-change seen by the bulk capacitors. The bulk filter

capacitor values are generally determined by the ESR

(effective series resistance) and capacitance requirements.

4CVOUT



I



--------------------------------

V

MAX

I ESR



–







(EQ. 23)

2.5 C



I



-----------------

V

MAX

I ESR



–

 V

–







(EQ. 24)

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