ISL6563CRZ datasheet(14/20 Pages) RENESAS

14 / 20 page

ISL6563

FN9126 Rev 8.00

Page 14 of 20

Jun 10, 2010

The above equation assumes the current through the lower

MOSFET is always positive; if so, the total power dissipated

in each lower MOSFET is approximated by the summation of

PLMOS1 and PLMOS2.

UPPER MOSFET POWER CALCULATION

In addition to rDS(ON) losses, a large portion of the upper-

MOSFET losses are switching losses, due to currents

conducted through the device while the input voltage is

present as VDS. Upper MOSFET losses can be divided into

separate components, separating the upper-MOSFET

switching losses, the lower-MOSFET body diode reverse

recovery charge loss, and the upper MOSFET rDS(ON)

conduction loss.

In most typical circuits, when the upper MOSFET turns off, it

continues to conduct the inductor current until the voltage at

the phase node falls below ground. Once the lower

MOSFET begins conducting (via its body diode or

enhancement channel), the current in the upper MOSFET

falls to zero. In Equation 12, the required time for this

commutation is t1and the associated power loss is PUMOS,1.

Similarly, the upper MOSFET begins conducting as soon as

it begins turning on. Assuming the inductor current is in the

positive domain, the upper MOSFET sees approximately the

input voltage applied across its drain and source terminals,

while it turns on and starts conducting the inductor current.

This transition occurs over a time t2, and the approximate

the power loss is PUMOS,2.

A third component involves the lower MOSFET’s reverse-

recovery charge, QRR. Since the lower MOSFET’s body

diode conducts the full inductor current before it has fully

switched to the upper MOSFET, the upper MOSFET has to

provide the charge required to turn off the lower MOSFET’s

body diode. This charge is conducted through the upper

MOSFET across VIN, the power dissipated as a result,

PUMOS,3 can be approximated using Equation 14:

Lastly, the conduction loss part of the upper MOSFET’s

power dissipation, PUMOS,4, can be calculated using

Equation 15:

In this case, of course, rDS(ON) is the ON-resistance of the

upper MOSFET.

The total power dissipated by the upper MOSFET at full load

can be approximated as the summation of these results.

Since the power equations depend on MOSFET parameters,

choosing the correct MOSFETs can be an iterative process

that involves repetitively solving the loss equations for

different MOSFETs and different switching frequencies until

converging upon the best solution.

Current Sensing

The resistor connected between the ISEN and VCC pins

determines the gain in the load-line regulation and the

channel-current balance loop. Select the value for this

resistor based on the room temperature rDS(ON) of the lower

MOSFETs and the full-load total output current, IFL.

Load Line Regulation Resistor

The load-line regulation resistor is labeled, R1 in Figure 1,

depends on the desired full-load droop voltage. At full load,

the current determined by RISEN is fed into the FB pin and

creates the output voltage droop across R1. Thus, the load

line regulation resistor can be computed using Equation 17:

Frequency Compensation

The load-line regulated converter behaves in a similar

manner to a peak-current mode controller because the two

poles at the output filter LC resonant frequency split with the

introduction of current information into the control loop. The

final location of these poles is determined by the system

function, the gain of the current signal, and the value of the

compensation components, R2 and C2.

The solution to the system equations can be fairly

complicated. Fortunately, there is a simple approximation

that comes very close to an optimal solution. Treating the

system as though it were a voltage mode regulator by

compensating the LC poles and the ESR zero of the voltage

mode approximation yields a solution that is always stable

with very close to ideal transient performance.

PUMOS 1, VIN

IOUT

-------------

IL PP

-------------





 t1

----









(EQ. 12)

PUMOS 2

VIN

IOUT

-------------

IL PP

-------------

–





 t2

----









(EQ. 13)

PUMOS 3,

VIN Qrr fS

(EQ. 14)

PUMOS 4,

rDS ON



IOUT

-------------





 2

IPP

----------

(EQ. 15)

RISEN

rDS ON



50 10 6

–



-----------------------

IFL

--------



(EQ. 16)

VDROOP 2RISEN



rDS ON

 IFL



-------------------------------------------------------

(EQ. 17)

FIGURE 8. COMPENSATION CONFIGURATION FOR ISL6563

CIRCUIT

COMP

VOUT

VDROOP

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