ISL6531CBZ datasheet(13/18 Pages) RENESAS

13 / 18 page

ISL6531

FN9053 Rev 2.00

Page 13 of 18

Aug 11, 2005

capacitor to high slew-rate transient loading. Unfortunately, ESL

is not a specified parameter. Work with your capacitor supplier

and measure the capacitor’s impedance with frequency to select

a suitable component. In most cases, multiple electrolytic

capacitors of small case size perform better than a single large

case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. Additionally, the output inductor for

the VTT regulator has to meet the minimum value criteria for

loop stability as described in the VTT Feedback Compensation

section. The inductor value determines the converter’s ripple

current and the ripple voltage is a function of the ripple current.

The ripple voltage and current are approximated by the

following equations:

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce the

converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6531 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

The response time to a transient is different for the application

of load and the removal of load. The following equations give

the approximate response time interval for application and

removal of a transient load:

where: ITRAN is the transient load current step, tRISE is the

response time to the application of load, and tFALL is the

response time to the removal of load. The worst case response

time can be either at the application or removal of load. Be

sure to check both of these equations at the minimum and

maximum output levels for the worst case response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic capacitors

for high frequency decoupling and bulk capacitors to supply the

current needed each time Q1 turns on. Place the small ceramic

capacitors physically close to the MOSFETs and between the

drain of Q1 and the source of Q2.

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum input

voltage and a voltage rating of 1.5 times is a conservative

guideline. The RMS current rating requirement for the input

capacitor of a buck regulator is approximately 1/2 the DC load

current.

The maximum RMS current required by the regulator may be

closely approximated through the following equation:

For a through hole design, several electrolytic capacitors may be

needed. For surface mount designs, solid tantalum capacitors can

be used, but caution must be exercised with regard to the

capacitor surge currentrating. These capacitors must be capable

of handling the surge-current at power-up. Some capacitor series

available from reputable manufacturers are surge current tested.

MOSFET Selection/Considerations

The ISL6531 requires two N-Channel power MOSFETs for each

PWM regulator. These should be selected based upon rDS(ON),

gate supply requirements, and thermal management

requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design factors.

The power dissipation includes two loss components; conduction

loss and switching loss. The conduction losses are the largest

component of power dissipation for both the upper and the lower

MOSFETs. These losses are distributed between the two

MOSFETs according to duty factor. The switching losses seen

when sourcing current will be different from the switching losses

seen when sinking current. The VDDQ regulator will only source

current while the VTT regulator can sink and source. When

sourcing current, the upper MOSFET realizes most of the

switching losses. The lower switch realizes most of the switching

losses when the converter is sinking current (see the equations

below). These equations assume linear voltage-current

transitions and do not adequately model power loss due the

reverse-recovery of the upper and lower MOSFET’s body diode.

The gate-charge losses are dissipated by the ISL6531 and don't

heat the MOSFETs. However, large gate-charge increases the

switching interval, tSW which increases the MOSFET switching

losses.

Ensure that both MOSFETs are within their maximum junction

temperature at high ambient temperature by calculating the

temperature rise according to package thermal-resistance

specifications. A separate heat sink may be necessary depending

I =

VIN - VOUT

fs x L

VOUT

VIN

VOUT = I x ESR

tRISE =

L x ITRAN

VIN - VOUT

tFALL =

L x ITRAN

VOUT

IRMS

MAX

VOUT

VIN

----------------

IOUT

MAX

------

VIN VOUT

–

Lfs



--------------------------------

VOUT

VIN

----------------







 2











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