HIP6004D datasheet(8/14 Pages) RENESAS

8 / 14 page

HIP6004D

FN4855 Rev 3.00

Page 8 of 14

July 13, 2005

Figure 5 shows the critical power components of the converter.

To minimize the voltage overshoot the interconnecting wires

indicated by heavy lines should be part of ground or power

plane in a printed circuit board. The components shown in

Figure 5 should be located as close together as possible.

Please note that the capacitors CIN and CO each represent

numerous physical capacitors. Locate the HIP6004D within 3

inches of the MOSFETs, Q1 and Q2. The circuit traces for the

MOSFETs’ gate and source connections from the HIP6004D

must be sized to handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

current paths on the SS pin and locate the capacitor, CSS

close to the SS pin because the internal current source is

only 10

A. Provide local VCC decoupling between VCC and

GND pins. Locate the capacitor, CBOOT as close as

practical to the BOOT and PHASE pins.

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(VOUT) is regulated to the Reference voltage level. The

error amplifier (Error Amp) output (VE/A) is compared with

the oscillator (OSC) triangular wave to provide a pulse-

width modulated (PWM) wave with an amplitude of VIN at

the PHASE node.

TABLE 1. OUTPUT VOLTAGE PROGRAM

PIN NAME

NOMINAL OUTPUT

VOLTAGE DACOUT

PIN NAME

NOMINAL OUTPUT

VOLTAGE DACOUT

VID4

VID3

VID2

VID1

VID0

VID4

VID3

VID2

VID1

VID0

111

1.475

110

1.100

111

1.500

101

1.125

110

1.525

100

1.150

110

1.550

011

1.175

101

1.575

010

1.200

101

1.600

001

1.225

100

1.625

000

1.250

100

1.650

111

1.275

011

1.675

110

1.300

011

1.700

101

1.325

010

1.725

100

1.350

010

1.750

011

1.375

001

1.775

010

1.400

001

1.800

001

1.425

000

1.825

000

1.450

000

1.850

NOTE: 0 = connected to GND or VSS, 1 = connected to VDD through pull-up resistors.

PGND

LGATE

UGATE

PHASE

VIN

VOUT

RETURN

HIP6004D

CIN

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+12V

HIP6004D

GND

VCC

BOOT

VOUT

PHASE

+VIN

CBOOT

CVCC

CSS

HIP6004D bảng dữ liệu(PDF) 8 Page - Renesas Technology Corp

HIP6004D bảng dữ liệu(HTML) 8 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

bảng dữ liệu tải về

Link URL