HIP6004D

FN4855 Rev 3.00

Page 6 of 14

July 13, 2005

GND (Pin 11)

Signal ground for the IC. All voltage levels are measured

with respect to this pin.

PGOOD (Pin 12)

PGOOD is an open collector output used to indicate the

status of the converter output voltage. This pin is pulled low

when the converter output is not within

10%of the

DACOUT reference voltage. Exception to this behavior is the

‘11111’ VID pin combination which disables the converter; in

this case PGOOD asserts a high level.

PHASE (Pin 13)

Connect the PHASE pin to the upper MOSFET source. This

pin is used to monitor the voltage drop across the MOSFET

for over-current protection. This pin also provides the return

path for the upper gate drive.

UGATE (Pin 14)

Connect UGATE to the upper MOSFET gate. This pin

provides the gate drive for the upper MOSFET.

BOOT (Pin 15)

This pin provides bias voltage to the upper MOSFET driver.

A bootstrap circuit may be used to create a BOOT voltage

suitable to drive a standard N-Channel MOSFET.

PGND (Pin 16)

This is the power ground connection. Tie the lower MOSFET

source to this pin.

LGATE (Pin 17)

Connect LGATE to the lower MOSFET gate. This pin

provides the gate drive for the lower MOSFET.

Provide a 12V bias supply for the chip to this pin.

OVP (Pin 19)

The OVP pin can be used to drive an external SCR in the

event of an overvoltage condition. Output rising 15% more

than the DAC-set voltage triggers a high output on this pin

and disables PWM gate drive circuitry.

RT (Pin 20)

This pin provides oscillator switching frequency adjustment.

200kHz switching frequency is increased according to the

following equation:

following equation:

Functional Description

Initialization

The HIP6004D automatically initializes upon receipt of power.

Special sequencing of the input supplies is not necessary. The

Power-On Reset (POR) function continually monitors the input

supply voltages. The POR monitors the bias voltage at the VCC

current protection). The POR function initiates soft start

operation after both input supply voltages exceed their POR

exceed the rising VCC threshold before POR initiates

operation.

Soft Start

The POR function initiates the soft start sequence. An internal

the SS pin to 4V. Soft start clamps the error amplifier output

(COMP pin) and reference input (+ terminal of error amp) to the

SS pin voltage. Figure 3 shows the soft start interval with

the SS voltage reaches the valley of the oscillator’s triangle

wave. The oscillator’s triangular waveform is compared to the

ramping error amplifier voltage. This generates PHASE pulses

of increasing width that charge the output capacitor(s). This

output voltage, the clamp on the reference input controls the

output voltage is in regulation. This method provides a rapid

and controlled output voltage rise. The PGOOD signal toggles

‘high’ when the output voltage (VSEN pin) is within

10% of

DACOUT. The 2% hysteresis built into the power good

comparators prevents PGOOD oscillation due to nominal

output voltage ripple.

Fs 200kHz

5 x 10

6



---------------------

+



Fs 200kHz 4 x 10

7



---------------------

–



0V

0V

0V

TIME (5ms/DIV)

SOFT-START

(1V/DIV)

OUTPUT

(1V/DIV)

VOLTAGE

PGOOD

(2V/DIV)

FIGURE 3. SOFT START INTERVAL