ISL68124IRAZ datasheet(18/46 Pages) RENESAS

18 / 46 page

ISL68124

FN8796 Rev.2.00

Page 18 of 46

June 16, 2017

Layout and Design Considerations

In addition to TB379, the following PCB layout and design

strategies are intended to minimize noise coupling and the

impact of board parasitic impedances on converter performance.

In addition, these strategies will optimize the heat dissipating

capabilities of the printed circuit board. This section highlights

some important practices, which should be followed during the

layout process.

Table 4 provides general guidance on best practices related to

pin noise sensitivity. Good engineering judgment is required to

implement designs based on criteria specific to the situation.

FIGURE 23. BLOCK DIAGRAM OF THERMAL MONITORING FUNCTION

TWARN

VCCS

TELEMETRY

CONTROL

TMAX

TEMP

SENSORS

TEMP

MONITOR

ADC

TMONx

DELTA

VBE

FIGURE 24. THERMAL WARNING TO TWARN

LOW OT THRESHOLD

HIGH OT THRESHOLD

PWM

PGOOD

TWARN

PWM

PGOOD

TWARN

HIGH OT THRESHOLD

LOW OT THRESHOLD

FIGURE 25. OVER-TEMPERATURE FAULT

TABLE 4. PIN DESIGN AND/OR LAYOUT CONSIDERATIONS

PIN NAME

NOISE

SENSITIVE

DESCRIPTION

VINSEN

Yes

Connects to the resistor divider between

VIN and GND (see Figure 16 on page 15).

Filter VINSEN with 10nF to GND

RGNDx

VSENx

Yes

Treat each of the remote voltage sense

pairs as differential signals in the PCB

layout. They should be routed side by side

on the same layer. They should not be

routed in proximity to noisy signals like

PWM or Phase. Tie to ground when not

used.

PGx

Open-drain. 3.3V maximum pull-up

voltage. Tie to ground when not used.

SCL, SDA,

SALRT

Yes

50kHz to 2MHz signal during

communication, pair up with SALRT and

route carefully. 20 mils spacing within

SDA, SALRT, and SCL; and more than

30 mils to all other signals. Refer to the

SMBus design guidelines and place

proper termination resistance for

impedance matching. Tie to ground when

not used.

TMONx

Yes

When diode sensing is used, VCCS is the

return path for the delta Vbe currents. Use

a separate VCCS route specifically for

diode temp sense. A filter capacitor no

greater than 500pF should be placed

between each TEMP pin and the VCCS pin

near the IC. Tie to ground when not used.

TWARN

Open-drain. 3.3V maximum pull-up

voltage.

VCC

Yes

Place at least 2.2µF MLCC decoupling

capacitor directly at the pin.

VCCS

Yes

Place 4.7µF MLCC decoupling capacitor

directly at the pin.

PWMx

Avoid routing near noise sensitive analog

lines such as current sense or voltage

sense.

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