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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ISL9216IRZ bảng dữ liệu(PDF) 20 Page - Renesas Technology Corp |
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ISL9216IRZ bảng dữ liệu(HTML) 20 Page - Renesas Technology Corp |
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20 / 34 page  ISL9216, ISL9217 FN6488 Rev 1.00 Page 20 of 34 November 2, 2007 . TABLE 10. WRITE ENABLE REGISTER (ADDR: 08H) BIT FUNCTION DESCRIPTION 7 FSETEN Enable discharge set writes When set to “1”, allows writes to the Feature Set register. When set to “0”, prevents writes to the Feature Set register (Addr: 07H). Default on initial power-up is “0”. 6 CHSETEN Enable charge set writes (ISL9216 only) When set to “1”, allows writes to the Charge Set register. When set to “0”, prevents writes to the Feature Set register (Addr: 06H). Default on initial power-up is “0”. 5 DISSETEN Enable discharge set writes (ISL9216 only) When set to “1”, allows writes to the Discharge Set register (Addr: 05H). When set to “0”, prevents writes to the Feature Set register. Default on initial power-up is “0”. 4UFLG3 User Flag 3 General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off. 3UFLG2 User Flag 3 General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off. 2 RESERVED Reserved for future expansion. 1 RESERVED Reserved for future expansion. 0 RESERVED Reserved for future expansion. FIGURE 1. BATTERY CONNECTION OPTIONS NOTE: MULTIPLE CELLS CAN BE CONNECTED IN PARALLEL VCELL7 VCELL6 VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VSS 12 CELLS CB7 CB6 CB5 CB4 CB3 CB2 CB1 VCELL7 VCELL6 VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VSS CB5 CB4 CB3 CB2 CB1 AO VCELL7 VCELL6 VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VSS 8 CELLS CB7 CB6 CB5 CB4 CB3 CB2 CB1 VCELL7 VCELL6 VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VSS CB5 CB4 CB3 CB2 CB1 AO VCELL7 VCELL6 VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VSS 11 CELLS CB7 CB6 CB5 CB4 CB3 CB2 CB1 VCELL7 VCELL6 VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VSS CB5 CB4 CB3 CB2 CB1 AO 9 CELLS VCELL7 VCELL6 VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VSS CB5 CB4 CB3 CB2 CB1 VCELL7 VCELL6 VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VSS 10 CELLS CB7 CB6 CB5 CB4 CB3 CB2 CB1 VCELL7 VCELL6 VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VSS CB5 CB4 CB3 CB2 CB1 AO VCELL7 VCELL6 VCELL5 VCELL4 VCELL3 VCELL2 VCELL1 VSS CB7 CB6 CB5 CB4 CB3 CB2 CB1 AO |
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