ISL9216, ISL9217

FN6488 Rev 1.00

Page 17 of 34

November 2, 2007

TABLE 5. ANALOG OUT CONTROL REGISTER (ADDR: 03H)

BITS

FUNCTION

DESCRIPTION

7UFLG1

User Flag 1

General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off.

6UFLG0

User Flag 0

General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off.

5:4

RESERVED

Reserved for future expansion

BIT 3

AO3

BIT 2

AO2

BIT 1

AO1

BIT 0

AO0

OUTPUT VOLTAGE

0

0

0

0

No Output (low power state)

0

0

0

1

VCELL1

0

0

1

0

VCELL2

0

0

1

1

VCELL3

0

1

0

0

VCELL4

0

1

0

1

VCELL5

0

1

1

0

VCELL6

0

1

1

1

VCELL7

1

0

0

0

External Temperature

1

0

0

1

Internal Temperature

1x1

x

Reserved

11

x

x

Reserved

TABLE 6. FET CONTROL REGISTER (ADDR: 04H)

BIT

FUNCTION

DESCRIPTION

7

SLEEP

Force Sleep

Setting this bit to “1” forces the device to go into a sleep condition. This turns off both FET outputs, the cell balance

outputs and the voltage regulator. This also resets the CFET, DFET, and CB7ON:CB1ON bits. The SLEEP bit is

automatically reset to “0” when the device wakes up. This does not reset the AO3:AO0 bits.

6LDMONEN

Turn on VMON

connection

(ISL9216 only)

Writing a “1” to this bit turns on the VMON circuit. Writing a “0” to this bit turns off the VMON circuit. As such, the

microcontroller has full control of the operation of this circuit.

5:2

RESERVED

Reserved for future expansion.

1CFET

(ISL9216 only)

Setting this bit to “1” turns on the charge FET.

Setting this bit to “0” turns off the charge FET.

This bit is automatically reset in the event of a charge overcurrent condition, unless the automatic response is disabled

by the DENOCC bit.

0DFET

(ISL9216 only)

Setting this bit to “1” turns on the discharge FET.

Setting this bit to “0” turns off the discharge FET.

This bit is automatically reset in the event of a discharge overcurrent or discharge short circuit condition, unless the

automatic response is disabled by the DENOCD or DENSCD bits.