CMV2000 datasheet(39/64 Pages) AMSCO

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Reference: CMV2000-datasheet-v3.8

CMV2000 v3 Datasheet

Page 38 of 63

5.9 INTERNAL PLL

5.9.1 ENABLE PLL

When using the internal PLL it is no longer required to input a high speed LVDS clock; the internal PLL will create it itself

depending on the register settings and the master input clock. Default the internal PLL is used. You can bypass and

disable the PLL with the following settings. Please note that when disabling the PLL, the LVDS clock input must be

enabled for the sensor to operate and the LVDS receiver current must have a value greater than 0.

Enable PLL

Default value

Description of the value

Pll_enable

113[0]

0: disables the PLL, saving some power

1: enables the PLL

Pll_bypass

115[0]

0: Use the internal PLL

1: Bypass the internal PLL, use when disabling PLL

LVDS clock input

enable

82[2]

0: disables the LVDS clock input

1: enables the LVDS clock input, use when disabling PLL

i_lvds_rec

74[3:0]

0: disables current for LVDS receiver

1-15: increases the current for the LVDS receiver, use

when disabling PLL

5.9.2 DATA RATE

During start-up or after a sequencer reset, the data rate can be changed if a lower speed than 480Mbps is desired. This

can be done by applying a lower master input clock (CLK_IN) to the sensor and uploading a new value in the PLL registers.

See section 3.5 for more details on the input clock. See section 3.7 and 3.8 for details on how and when the data rate

can be changed.

PLL range

CLK_IN range [MHz]

PLL_range

PLL_OUT_FRE

PLL_IN_FRE

From – To

116[7]

116[6:4]

114[1:0]

30 - 48

20 - 30

15 - 20

10 - 15

7.5 - 10

5 - 7.5

5.10 10-BIT OR 12-BIT MODE

The CMV2000 has the possibility to send 12 bits or 10 bits per pixel. The end user can select the desired resolution by

programming the corresponding sequencer register.

10-bit or 12-bit mode

Default value

Description of the value

Bit_mode

111[0]

0: 12 bits per pixel

1: 10 bits per pixel

ADC_Resolution

112[1:0]

0: 10 bits per pixel

1: 11 bits per pixel

2: 12 bits per pixel

PLL_load

117[7:0]

10 bit: set to 8

12 bit: set to 4

PLL_div

116[3:0]

10 bit: set to 9

12 bit: set to 11

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