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IPAC-X bảng dữ liệu(PDF) 39 Page - Infineon Technologies AG |
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IPAC-X bảng dữ liệu(HTML) 39 Page - Infineon Technologies AG |
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39 / 270 page ![]() IPAC-X PSB/PSF 21150 Description of Functional Blocks Data Sheet 39 2003-01-30 3.2.2 Parallel Microcontroller Interface The 8-bit parallel microcontroller interface with address decoding on chip allows easy and fast microcontroller access. The parallel interface of the IPAC-X provides three types of mP buses which are selected via pin ALE. The bus operation modes with corresponding pins are listed in Table 5. The occurrence of an edge on ALE, either positive or negative, at any time during the operation immediately selects the interface type (3). A return to one of the other interface types is possible only if a hardware reset is issued. Note: If the multiplexed address/data bus type (3) is selected, the unused address pins A0-A7 must be tied to VDD. A read/write access to the IPAC-X registers can be done in multiplexed or non- multiplexed mode: • In non-multiplexed mode the register address must be applied to the address bus (A0- A7) for the data access via the data bus (AD0-AD7). • In multiplexed mode the address on the address/data bus (AD0-AD7) is latched in by ALE before a data read/write access via the same bus is performed. The IPAC-X provides two different ways to address the register contents which is selected with the AMOD pin (’0’ = direct mode, ’1’ = indirect mode). Figure 10 illustrates both register addressing modes. Direct address mode (AMOD = ’0’): The register address to be read or written is directly set in the way described above. Indirect address mode (AMOD = ’1’): Only the LSB of the address is used to select either the address register (A0 = ’0’) or the data register (A0 = ’1’). The microcontroller writes the register address to the ADDRESS register before it reads/writes data from/to the corresponding DATA register. In indirect address mode the IPAC-X evaluates no address line except the least significant address bit. The remaining address lines must not be left open but have to be tied to logical ’1’. Table 5 Bus Operation Modes Bus Mode Pin ALE Control Pins (1) Motorola VDD CS, R/W, DS (2) Siemens/Intel non-multiplexed VSS CS, WR, RD (3) Siemens/Intel multiplexed Edge CS, WR, RD, ALE |
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