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HMC7950LS6 bảng dữ liệu(PDF) 13 Page - Analog Devices |
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HMC7950LS6 bảng dữ liệu(HTML) 13 Page - Analog Devices |
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13 / 16 page ![]() Data Sheet HMC7950 Rev. A | Page 13 of 16 APPLICATIONS INFORMATION Capacitive bypassing is recommended for VDD, as shown in the typical application circuit in Figure 39. Gain control is possible through the application of a dc voltage to VGG2. If gain control is used, capacitive bypassing of VGG2 is recommended as shown in the typical application circuit. If gain control is not used, VGG2 can be either left open or capacitively bypassed as shown in Figure 39. The recommended bias sequence during power-up is as follows: 1. Set VDD to 5.0 V (this results in an IDD near its specified typical value). 2. If the gain control function is to be used, apply a voltage within the range of −2.0 V to +2.6 V to VGG2 until the desired gain setting is achieved. 3. Apply the RF input signal. The recommended bias sequence during power-down is as follows: 1. Turn off the RF input signal. 2. Remove the VGG2 voltage, or set it to 0 V. 3. Set VDD to 0 V. Power-up and power-down sequences can differ from the ones described, although care must always be taken to ensure adherence to the values shown in the Absolute Maximum Ratings section. Unless otherwise noted, all measurements and data shown were taken using the typical application circuit as configured on the HMC7950 evaluation board. The bias conditions shown in the Specifications section are recommended to optimize the overall performance. Operation using other bias conditions may result in performance that differs from the data shown in this data sheet. Figure 39. Typical Application Circuit VDD 10nF 4.7µF 100pF + 10nF 4.7µF VGG2 100pF RFOUT RFIN PACKAGE BASE GND 1 2 3 11 10 9 16 12 13 14 15 4 8 7 6 5 |
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