LT1351 datasheet(13/20 Pages) LINER

13 / 20 page

LT6274/LT6275

6275fa

For more information www.linear.com/LT6275

large slewing outputs, and the increased power is propor-

tional to the magnitude of the differential input voltage and

the percent of the time that the inputs are apart. Measure

the average supply current for the application in order to

calculate the power dissipation.

Capacitive Loading

The LT6274/LT6275 are stable with any capacitive load.

As previously stated in the Circuit Operation section of this

data sheet, this is accomplished by dynamically sensing

the load-induced output pole and adjusting the compensa-

tion at the amplifier’s internal gain node. As the capacitive

load increases, the bandwidth will decrease. The phase

margin may increase or decrease with different capaci-

tive loads, and so there may be peaking in the frequency

domain and overshoot in the transient response for some

capacitive loads as shown in the Typical Performance

curves. The Small-Signal Step Response curve with 10nF

load shows 30% overshoot. For large load capacitance,

the slew rate of the LT6274/LT6275 can be limited by

the output current available to charge the load capacitor

according to:

SR=

ISC

The Large-Signal Step Response with 10nF load shows

the output slew rate being limited to 9V/µs by the output

short-circuit current. Coaxial cable can be driven directly,

but for best pulse fidelity the cable should be properly

terminated by placing a resistor of value equal to the char-

acteristic impedance of the cable (e.g. 50Ω) in series with

the output. The other end of the cable should be termi-

nated with the same value resistor to ground.

Layout and Passive Components

The LT6274/LT6275 are easy to use and tolerant of less

than ideal layouts. For maximum performance use a

ground plane, short lead lengths, and RF-quality ceramic

bypass capacitors (0.01µF to 0.1µF). For high drive cur-

rent applications use low ESR bypass capacitors (1µF to

10µF ceramic or tantalum). The resistance of the parallel

combination of the feedback resistor and gain setting

resistor on the inverting input combines with the total

capacitance on that node, CIN, to form a pole which can

cause peaking or oscillations. If feedback resistors greater

than 5k are used, a parallel capacitor of value

CF > RG × CIN/RF

should be used to cancel the input pole and optimize

dynamic performance. For unity-gain applications where

a large feedback resistor is used, CF should be greater

than or equal to CIN.

Power Dissipation

The LT6274/LT6275 combine high speed and large out-

put drive in a small package. Because of the wide sup-

ply voltage range, it is possible to exceed the maximum

junction temperature under certain conditions. Maximum

junction temperature (TJ) is calculated from the ambient

temperature (TA), the device’s power dissipation (PD),

and the thermal resistance of the device (θJA) as follows:

TJ = TA + (PD × θJA)

Worst case power dissipation occurs at the maximum

supply current and when the output voltage is at 1/2 of

either V+ or V– (on split rails), or at the maximum out-

put swing (if less than 1/2 of the rail voltage). Therefore

PDMAX (per amplifier) is:

PDMAX = (V+ – V–)(ISMAX) + (V+/2)2/RL

Example: For an LT6274 with thermal resistance of

215°C/W, operating on ±15V supplies and driving a 1kΩ

load to 7.5V, the maximum power dissipation is calculated

to be:

PDMAX = (30V)(2.3mA) + (7.5V)2/1kΩ = 125mW

This leads to a die temperature rise above ambient of:

TRISE = (125mW)(215°C/W) = 27°C

This implies that the maximum ambient temperature at

which the LT6274 should operate under the above condi-

tions is:

TA = 150°C – 27°C = 123°C

APPLICATIONS INFORMATION

LT1351 bảng dữ liệu(PDF) 13 Page - Linear Technology

LT1351 bảng dữ liệu(HTML) 13 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

bảng dữ liệu tải về

Link URL