LTM4609 datasheet(21/38 Pages) LINER

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LTM4636-1

46361fa

For more information www.linear.com/LTM4636-1

APPLICATIONS INFORMATION

RUNP and RUNC Enable

The RUNP pin is used to enable the 5V PVCC supply that

powersthepowerdriverstageandenablesthepowerstage

~1ms later. The RUNC pin is used to enable the control

section that drives the power stage. The RUNP needs to be

enabled first, and then RUNC. RUNP has a 0.85V threshold

and can be connected to the input voltage and RUNC has

a 1.35V threshold and a 10k resistor to ground. See the

BlockDiagramfordetails.A0.1µFcapacitorfromtheRUNC

pin to ground is used to set the delay for RUNC enable.

INTVCC and PVCC Regulators

The LTM4636-1 has an internal low dropout regulator

from VIN called INTVCC. This regulator output has a 4.7F

ceramic capacitor internal. This regulator powers the

control section. The PVCC 5V regulator supplies power

to the power MOSFET driver stage. An additional 50mA

can be used from this 5V PVCC supply for other needs.

The input supply source resistance needs to be very low

in order to minimize IR drops when operating from a 5V

inputsource.Dependingontheoutputvoltageandcurrent,

the input supply can source large current,and PVCC 5V

regulator needs a minimum 4.7V supply. Additional input

capacitance maybe needed for 5V inputs to limit the input

droop.

Stability Compensation

The LTM4636-1 has already been internally compensated

when COMPB is tied to COMPA for all output voltages.

Table 5 is provided for most application requirements.

For specific optimized requirements, disconnect COMPB

from COMPA, and use LTpowerCAD to perform specific

control loop optimization. Then select the desired external

compensation and output capacitance for the desired

optimized response.

SW Pins

The SW pins are generally for testing purposes by moni-

toring these pins. These pins can also be used to dampen

out switch node ringing caused by LC parasitic in the

switched current paths. Usually a series R-C combina-

tion is used called a snubber circuit. The resistor will

dampen the resonance and the capacitor is chosen to

only affect the high frequency ringing across the resistor.

If the stray inductance or capacitance can be measured or

approximated then a somewhat analytical technique can

be used to select the snubber values. The inductance is

usually easier to predict. It combines the power path board

inductance in combination with the MOSFET interconnect

bond wire inductance.

First the SW pin can be monitored with a wide bandwidth

scope with a high frequency scope probe. The ring fre-

quency can be measured for its value. The impedance Z

can be calculated:

Z(L) = 2πfL,

where f is the resonant frequency of the ring, and L is the

total parasitic inductance in the switch path. If a resistor

is selected that is equal to Z, then the ringing should be

dampened. The snubber capacitor value is chosen so that

its impedance is equal to the resistor at the ring frequency.

Calculated by: Z(C) = 1/(2πfC). These values are a good

place to start with. Modification to these components

should be made to attenuate the ringing with the least

amount of power loss. A recommended value of 2.2 in

series with 2200pF to ground should work for most ap-

plications. See Figure 19 for layout guidelines. The 2.2

resistor should be an 0805 size.

Thermal Considerations and Output Current Derating

The thermal resistances reported in the Pin Configuration

section of the data sheet are consistent with those param-

eters defined by JESD51-12 and are intended for use with

finite element analysis (FEA) software modeling tools that

leverage the outcome of thermal modeling, simulation,

and correlation to hardware evaluation performed on a

µModule package mounted to a hardware test board.

The motivation for providing these thermal coefficients

in found in JESD51-12 (“Guidelines for Reporting and

Using Electronic Package Thermal Information”).

Manydesignersmayopttouselaboratoryequipmentanda

testvehiclesuchasthedemoboardtopredicttheµModule

regulator’s thermal performance in their application at

various electrical and environmental operating conditions

to compliment any FEA activities. Without FEA software,

the thermal resistances reported in the Pin Configuration

section are, in and of themselves, not relevant to providing

guidance of thermal performance; instead, the derating

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