SIT3521 datasheet(32/44 Pages) SITIME

32 / 44 page

Rev 0.90

Page 32 of 44

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SiT3521 1 to 340 MHz Elite™ I2C/SPI Programmable Oscillator

PRELIMINARY

10 I2C Operation

10.1. I2C protocol

Data valid

The SDA line must be stable during the high period of the

SCLK. SDA transitions are allowed only during SCLK low

level for data communication. Only one transition is

allowed during low SCLK pulse to communicate one bit of

data. Figure 28 shows the detailed timing diagram.

START and STOP conditions

The idle I2C bus state occurs when both SCLK and SDA

are not being driven by any master and are therefore in a

logic HI state due to the pull up resistors. Every

transaction begins with a START (S) signal and ends with

a STOP (P) signal. A START condition is defined by a

high to low transition on the SDA while SCLK is high. A

STOP condition is defined by a low to high transition on

the SDA while SCLK is high. START and STOP conditions

are always generated by master. This slave module also

supports repeated START (Sr) condition which is same as

START condition instead of STOP condition (Blue color

line shows repeated START in Figure 29).

SDA

SCLK

data line stable:

data valid

change of data

allowed

setup time

Figure 28. Data and clock timing relation in I2C bus

SDA

SCLK

START Condition

STOP Condition

hold time

setup time

hold time

Figure 29. START and STOP (or repeated START) condition

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