CS5530A datasheet(141/259 Pages) NSC

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4.1

PCI CONFIGURATION SPACE AND ACCESS METHODS

Configuration cycles are generated in the processor. All

configuration registers in the CS5530A are accessed

through the PCI interface using the PCI Type One Configu-

ration Mechanism. This mechanism uses two DWORD I/O

locations at 0CF8h and 0CFCh. The first location (0CF8h)

references the Configuration Address Register. The sec-

ond location (0CFCh) references the Configuration Data

To access PCI configuration space, write the Configuration

Address (0CF8h) Register with data that specifies the

CS5530A as the device on PCI being accessed, along with

the configuration register offset. On the following cycle, a

read or write to the Configuration Data Register (CDR)

causes a PCI configuration cycle to the CS5530A. BYTE,

WORD, or DWORD accesses are allowed to the CDR at

0CFCh, 0CFDh, 0CFEh, or 0CFFh.

The CS5530A has six configuration register sets, one for

each function (F0-F4) and USB (PCIUSB). Base Address

Registers (BARs) in the PCI header registers are pointers

for additional I/O or memory mapped configuration regis-

ters.

Table 4-1 shows the PCI Configuration Address Register

(0CF8h) and how to access the PCI header registers.

Table 4-1. PCI Configuration Address Register (0CF8h)

Configuration

Space Mapping

RSVD

Bus Number

Device Number

Function

Index

DWORD

1 (Enable)

000 0000

0000 0000

xxxx x (Note)

xxx

xxxx xx

00 (Always)

Function 0 (F0): Bridge Configuration Register Space

80h

0000 0000

1001 0 or 1000 0

000

Index

Function 1 (F1): SMI Status and ACPI Timer Register Space

80h

0000 0000

1001 0 or 1000 0

001

Index

Function 2 (F2): IDE Controller Register Space

80h

0000 0000

1001 0 or 1000 0

010

Index

Function 3 (F3): XpressAUDIO Subsystem Register Space

80h

0000 0000

1001 0 or 1000 0

011

Index

Function 4 (F4): Video Controller Register Space

80h

0000 0000

1001 0 or 1000 0

100

Index

PCIUSB: USB Controller Register Space

80h

0000 0000

1001 1 or 1000 1

000

Index

Note: The device number depends upon the strapping of pin H26 (HOLD_REQ#) during POR.

Strap pin H26 low: IDSEL = AD28 for Chipset Register Space and AD29 for USB Register Space

Strap pin H26 high: IDSEL = AD26 for Chipset Register Space and AD27 for USB Register Space

The strapping of pin H26 can be read back in F0 Index 44h[6].

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