CS5530A datasheet(139/259 Pages) NSC

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Functional Description (Continued)

3.9.2

USB Host Controller

In the USB core is the operational control block. It is

responsible for the host controller's operational states

(Suspend, Disable, Enable), special USB signals (Reset,

Resume), status, interrupt control, and host controller con-

figuration.

The host controller interface registers are memory mapped

registers, mapped by USB F0 Index 10h (Base Address

rized in Table 3-78. For bit definitions, refer to Table 4-26

"USB BAR+Memory Offset xxh: USB Controller Registers"

on page 213.

3.9.3

USB Power Management

At this time, USB supports minimal system level power

management features. The only power management fea-

ture implemented is the disabling of the USB clock genera-

tor in USB Suspend state. Additional power management

features require slight modifications.

The design supports PCICLK frequencies from 0 to 33

MHz. Synchronization between the PCI and USB clock

domains is frequency independent. Remote wakeup of

USB is asynchronously implemented from the USB Ports

to PCI INTA#.

The design needs USBCLK to be operational at all times. If

it is necessary to stop the 48 MHz clock, the system design

requires that the signal used to enable/disable the USB

clock generators is also used to wake the 48 MHz clock

source. Currently, the RemoteWakeupConnected and

RemoteWakeupEnable bits in the HcControl register are

not implemented.

Table 3-78. USB Controller Registers

USB BAR+

Memory

Offset

Type

Name

00h-03h

R/W

HcRevision

04h-07h

R/W

HcControl

08h-0Bh

R/W

HcCommandStatus

0Ch-0Fh

R/W

HcInterruptStatus

10h-13h

R/W

HcInterruptEnable

14h-17h

R/W

HcInterruptDisable

18h-1Bh

R/W

HcHCCA

1Ch-1Fh

R/W

HcPeriodCurrentED

20h-23h

R/W

HcControlHeadED

24h-27h

R/W

HcControlCurrentED

28h-2Bh

R/W

HcBulkHeadED

2Ch-2Fh

R/W

HcBulkCurrentED

30h-33h

R/W

HcDoneHead

34h-37h

R/W

HcFmInterval

38h-3Bh

HcFrameRemaining

3Ch-3Fh

HcFmNumber

40h-43h

R/W

HcPeriodicStart

44h-47h

R/W

HcLSThreshold

48h-4Bh

R/W

HcRhDescriptorA

4Ch-4Fh

R/W

HcRhDescriptorB

50h-53h

R/W

HcRhStatus

54h-57h

R/W

HcRhPortStatus[1]

58h-5Bh

R/W

HcRhPortStatus[2]

5Ch-5Fh

Reserved

60h-9Fh

Reserved

100h-103h

R/W

HceControl

104h-107h

R/W

HceInput

108h-10Dh

R/W

HceOutput

10Ch-10Fh

R/W

HceStatus

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