PIC12CE673-04SLASHP datasheet(14/129 Pages) MICROCHIP

14 / 129 page

PIC12C67X

DS30561B-page 14

Bank 1

80h(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

81h

OPTION

GPPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

82h(1)

PCL

Program Counter’s (PC) Least Significant Byte

0000 0000

83h(1)

STATUS

IRP(4)

RP1(4)

RP0

ZDC

0001 1xxx

000q quuu

84h(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRIS

—

GPIO Data Direction Register

--11 1111

86h

—

Unimplemented

—

87h

—

Unimplemented

—

88h

—

Unimplemented

—

89h

—

Unimplemented

—

8Ah(1,2)

PCLATH

—

Write Buffer for the upper 5 bits of the PC

---0 0000

8Bh(1)

INTCON

GIE

PEIE

T0IE

INTE

GPIE

T0IF

INTF

GPIF

0000 000x

0000 000u

8Ch

PIE1

—ADIE

—

-0-- ----

8Dh

—

Unimplemented

—

8Eh

PCON

—

—POR

—

---- --0-

---- --u-

8Fh

OSCCAL

CAL3

CAL2

CAL1

CAL0

CALFST

CALSLW

—

0111 00--

uuuu uu--

90h

—

Unimplemented

—

91h

—

Unimplemented

—

92h

—

Unimplemented

—

93h

—

Unimplemented

—

94h

—

Unimplemented

—

95h

—

Unimplemented

—

96h

—

Unimplemented

—

97h

—

Unimplemented

—

98h

—

Unimplemented

—

99h

—

Unimplemented

—

9Ah

—

Unimplemented

—

9Bh

—

Unimplemented

—

9Ch

—

Unimplemented

—

9Dh

—

Unimplemented

—

9Eh

—

Unimplemented

—

9Fh

ADCON1

—

PCFG2

PCFG1

PCFG0

---- -000

TABLE 4-1:

PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-on

Reset

Value on

all other

Resets(3)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.

5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.

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