PIC12CE673-04SLASHP datasheet(35/129 Pages) MICROCHIP

35 / 129 page

DS30561B-page 35

PIC12C67X

FIGURE 6-3:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 6-4:

ACKNOWLEDGE TIMING

6.2

Device Addressing

After generating a START condition, the processor

transmits a control byte consisting of a EEPROM

address and a Read/Write bit that indicates what type

of operation is to be performed. The EEPROM address

consists of a 4-bit device code (1010) followed by three

don’t care bits.

The last bit of the control byte determines the operation

to be performed. When set to a one, a read operation

is selected, and when set to a zero, a write operation is

selected (Figure 6-5). The bus is monitored for its cor-

responding EEPROM address all the time. It generates

an acknowledge bit if the EEPROM address was true

and it is not in a programming mode.

FIGURE 6-5:

CONTROL BYTE FORMAT

(A)

(B)

(C)

(D)

(A)

(C)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL

123

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this

point so the Transmitter can continue

sending data.

Data from transmitter

SDA

Acknowledge

Bit

SACK

R/W

Device Select

Bits

Don’t Care

Bits

EEPROM Address

Acknowledge Condition

Start Condition

Read/Write Bit

PIC12CE673-04/P bảng dữ liệu(PDF) 35 Page - Microchip Technology

PIC12CE673-04/P bảng dữ liệu(HTML) 35 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL